代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/461789/7219863
udo ss.udo
-- ProjNav VHDL simulation template: ss.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/461789/7220064
vhdsim_par led.vhdsim_par
led.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: ModelSim SE (VHDL)
www.eeworm.com/read/460722/7242525
qmsg cmp.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
www.eeworm.com/read/458598/7293592
npl keyb.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT keyb
DESIGN keyb
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLE
www.eeworm.com/read/458598/7293593
log coregen.log
# Xilinx CORE Generator 6.1i
# User = tmp
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\USERS\keyb\coregen.log
NEWPROJECT .
SETPROJECT .
# busf
www.eeworm.com/read/453446/7420378
sth sources.sth
[Files List]
c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S
c:\program files\aldec\active-vhdl\vlib\ieee\src\stdlogic.vhd=S
c:\my designs\comparator\src\VHDL code1.vhd=S
www.eeworm.com/read/453446/7420380
lib~ contents.lib~
3
~E
comp4b
c:\my designs\comparator\src\VHDL code1.vhd
4
~A
behav
c:\my designs\comparator\src\VHDL code1.vhd
8
www.eeworm.com/read/453446/7420404
sth sources.sth
[Files List]
c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S
c:\program files\aldec\active-vhdl\vlib\ieee\src\stdlogic.vhd=S
c:\my designs\decoder\src\VHDL code2.vhd=S
www.eeworm.com/read/453446/7420407
lib~ contents.lib~
3
~E
dec24d
c:\my designs\decoder\src\VHDL code2.vhd
3
~A
dataflow
c:\my designs\decoder\src\VHDL code2.vhd
7
www.eeworm.com/read/453446/7420429
sth sources.sth
[Files List]
c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S
c:\program files\aldec\active-vhdl\vlib\ieee\src\stdlogic.vhd=S
c:\my designs\dff\src\VHDL code4.vhd=S