cmp.tan.qmsg

vhdl 基础例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 15:06:40 2006 " "Info: Processing started: Sat Feb 18 15:06:40 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] c\[2\] 10.745 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"c\[2\]\" is 10.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[0\] 1 PIN PIN_71 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'a\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" Compiler "cmp" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/" "" "" { a[0] } "NODE_NAME" } "" } } { "cmp.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/cmp.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.425 ns) + CELL(0.200 ns) 4.757 ns LessThan~349 2 COMB LC_X13_Y7_N1 1 " "Info: 2: + IC(3.425 ns) + CELL(0.200 ns) = 4.757 ns; Loc. = LC_X13_Y7_N1; Fanout = 1; COMB Node = 'LessThan~349'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" Compiler "cmp" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/" "" "3.625 ns" { a[0] LessThan~349 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.262 ns LessThan~350 3 COMB LC_X13_Y7_N2 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 5.262 ns; Loc. = LC_X13_Y7_N2; Fanout = 1; COMB Node = 'LessThan~350'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" Compiler "cmp" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/" "" "0.505 ns" { LessThan~349 LessThan~350 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.767 ns LessThan~351 4 COMB LC_X13_Y7_N3 4 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.767 ns; Loc. = LC_X13_Y7_N3; Fanout = 4; COMB Node = 'LessThan~351'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" Compiler "cmp" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/" "" "0.505 ns" { LessThan~350 LessThan~351 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(2.322 ns) 10.745 ns c\[2\] 5 PIN PIN_117 0 " "Info: 5: + IC(2.656 ns) + CELL(2.322 ns) = 10.745 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" Compiler "cmp" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/" "" "4.978 ns" { LessThan~351 c[2] } "NODE_NAME" } "" } } { "cmp.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/cmp.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.054 ns 37.73 % " "Info: Total cell delay = 4.054 ns ( 37.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.691 ns 62.27 % " "Info: Total interconnect delay = 6.691 ns ( 62.27 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp_cmp.qrpt" Compiler "cmp" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/db/cmp.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/基础实验/四位比较器/" "" "10.745 ns" { a[0] LessThan~349 LessThan~350 LessThan~351 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.745 ns" { a[0] a[0]~combout LessThan~349 LessThan~350 LessThan~351 c[2] } { 0.000ns 0.000ns 3.425ns 0.305ns 0.305ns 2.656ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.200ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:06:41 2006 " "Info: Processing ended: Sat Feb 18 15:06:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}