coregen.log

来自「fifo code. i have adde the code for key 」· LOG 代码 · 共 23 行

# Xilinx CORE Generator 6.1i
# User = tmp
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\USERS\keyb\coregen.log
NEWPROJECT .
SETPROJECT .
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\USERS\keyb
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\USERS\keyb
Set current Project to E:\USERS\keyb
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1038
XIPCPJSENDCORES spartan2