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找到约 10,000 项符合「VHDL」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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log coregen.log

# Xilinx CORE Generator 6.2.01i # User = lijintao Initializing default project... Loading plug-ins... All runtime messages will be recorded in D:\FPGA\仿真\Divider\coregen.log NEWPROJECT . SETPROJ
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www.eeworm.com/read/364631/9902625

rpt proj.asm.rpt

Assembler report for Proj Tue Dec 05 14:53:49 2006 Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Lega
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www.eeworm.com/read/167697/9955519

txt 将16进制转化为std_logic.txt

VHDL: Converting a Hexadecimal Value to a Standard Logic Vector This example shows how to convert a hexadecimal value to a std_logic_vector. It is shown in both VHDL '87 (IEEE Std 1076-1987) and
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www.eeworm.com/read/167058/9982833

log coregen.log

# Xilinx CORE Generator 6.1i # User = Administrator Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\Create-SOPC1000X\ISE\Exp4-Clock\coregen.log # b
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www.eeworm.com/read/361921/10028982

rpt a8254.map.rpt

Analysis & Synthesis report for a8254 Wed Sep 03 10:36:58 2008 Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------------
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www.eeworm.com/read/360684/10082105

npl i2c.npl

JDF F // Created by Project Navigator ver 1.0 PROJECT Untitled DESIGN i2c Normal DEVFAM xpla3 DEVFAMTIME 1039799570 DEVICE xcr3256xl DEVICETIME 1039799570 DEVPKG TQ144 DEVPKGTIME 315558000 D
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www.eeworm.com/read/359174/10162726

udo test2_v.udo

-- ProjNav VHDL simulation template: test2_v.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/359174/10162908

udo test3_v.udo

-- ProjNav VHDL simulation template: test3_v.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/359174/10163260

udo test1_v.udo

-- ProjNav VHDL simulation template: test1_v.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/358923/10175239

qmsg ledwater.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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