coregen.log

数字计时器

# Xilinx CORE Generator 6.1i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\Create-SOPC1000X\ISE\Exp4-Clock\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\Create-SOPC1000X\ISE\Exp4-Clock
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\Create-SOPC1000X\ISE\Exp4-Clock
SETPROJECT .
Set current Project to E:\Create-SOPC1000X\ISE\Exp4-Clock
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1033
XIPCPJSENDCORES virtex2