coregen.log

来自「本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.」· LOG 代码 · 共 23 行

# Xilinx CORE Generator 6.2.01i
# User = lijintao
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\FPGA\仿真\Divider\coregen.log
NEWPROJECT .
SETPROJECT .
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=D:\FPGA\仿真\Divider
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=D:\FPGA\仿真\Divider
Set current Project to D:\FPGA\仿真\Divider
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1032
XIPCPJSENDCORES spartan2