代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/212909/15145387

rpt djdplj_top.map.rpt

Analysis & Synthesis report for djdplj_top Sun May 20 17:10:17 2007 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version --------------------- ; Table of Contents ; --------------------
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www.eeworm.com/read/212430/15156275

_verilog_hintfile

#OPTIONS:"|-bldtbl|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-autosm|-fid2|-sharing|on|-encrypt|-ui|-lite|-pro|-ram|-ignore_undefined_lib|-ll|2000|-lib|work|-lib|work|-lib|work|-l
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www.eeworm.com/read/212353/15159105

npl decdor_38.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT decdor_38 DESIGN decdor_38 DEVFAM spartan2 DEVFAMTIME 0 DEVICE xc2s100 DEVICETIME 1178852124 DEVPKG pq208 DEVPKGTIME 0 DEVSPEED -5 DEVS
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www.eeworm.com/read/210231/15203914

log __projnav.log

Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file e:/vhdl/dig_clk/second.vhdl in Library work. ERROR:HDLPar
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www.eeworm.com/read/210231/15203943

lst netlist.lst

F:\FPGA\VHDL\waitpast\dig_clk_lcd\digclk.ngc 1179308678 OK
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www.eeworm.com/read/208860/15234005

ds mips.ds

/* Batch file for Synth use "fpga_shell -f this_filename" */ /* String for top level of design - use all lowercase! */ /* Signal names are case sensitive in ZyCAD but not VHDL! */ TOP=top_spim des
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www.eeworm.com/read/172417/5386925

opt simgen.opt

-p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti
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www.eeworm.com/read/167507/5459676

opt simgen.opt

-p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti
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www.eeworm.com/read/155551/5621050

opt simgen.opt

-p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti
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www.eeworm.com/read/154801/5634588

opt simgen.opt

-p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti
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