mips.ds

麻省理工的一个实验室实现的MIPS IP CORE

/* Batch file for Synth use "fpga_shell -f this_filename" */
/* String for top level of design - use all lowercase! */
/* Signal names are case sensitive in ZyCAD but not VHDL! */
TOP=top_spim
designer="G.P.Burdell"
company="Ga Tech"
xnfout_library_version="2.0.0"
/* Analyze & elaborate any submodules first then do top level */
/* analyze -format vhdl Sub_modulename(s).vhd */
/* elaborate Sub_modulename(s) */
analyze -format vhdl ifetch.vhd
elaborate IFETCH
analyze -format vhdl control.vhd
elaborate CONTROL
analyze -format vhdl idecode.vhd
elaborate IDECODE
analyze -format vhdl execute.vhd
elaborate EXECUTE
analyze -format vhdl dmemory.vhd
elaborate DMEMORY
analyze -format vhdl TOP +".vhd"
elaborate TOP
/* Unique names for multiple submodules if needed */
uniquify
/* Add pads to the design. Make sure the current 
   design is the top-level module.                  */
current_design TOP
   set_port_is_pad "*" 
   set_pad_type -slewrate HIGH all_outputs()
/* The next lines needed for bidir. I/O lines if any */
/*   remove_attribute(P_XX) port_is_pad   */
/*   set_dont_touch {list of Bidirectional Input ports or chips} */
/*   set_dont_touch {list of Bidirectional Output ports or chips} */   
/* Make I/O into pads(pins) on Xilinx chip */
insert_pads
/* Set constraints */
remove_constraint -all
/* clock max? */
/* Optimize */
compile -map_effort med
report_fpga > TOP + ".fpga"
report_timing > TOP + ".timing"
/* Save synth result */
write -format db -hier -output TOP + ".db"
/* Change CLBs to gates */
replace_fpga
set_attribute TOP "part" -type string "4005pc84-5"
set_attribute find(design,"*") "xnfout_write_map_symbols" -type boolean FALSE
set_attribute find(design,"*") "xnfout_use_blknames" -type boolean FALSE 
/* Save sxnf file - for multi hierarchy change next line to */
/* write -format xnf -hier -output TOP + ".sxnf" */
write -format xnf  -output TOP + ".sxnf"
/*write_sge */
exit