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找到约 10,000 项符合「VHDL」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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rpt ex09.rpt

Project Information d:\vhdl_ex\ex09.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 10/29/2003 10:58:46 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/149028/12408355

vhd 56_prefetch.vhd

--**VHDL************************************************************* -- -- SRC-MODULE : PREFETCH -- NAME : prefetch.vhdl -- VERSION : 1.0 -- -- PURPOSE : Architecture of PREFETCH b
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log coregen.log

# Xilinx CORE Generator 6.3.03i # User = 王毅诚 Initializing default project... Loading plug-ins... All runtime messages will be recorded in D:\Xilinx\bin\200404015010成功\coregen.log # busformat=BusF
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mpf uart.mpf

[Library] ; Altera specific primitive library mappings vital2000 = $MODEL_TECH/../vital2000 ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog std = $MODEL_TECH/../std std_develope
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hif cout_top.hif

Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version 35 1763 OFF OFF OFF OFF OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Libr
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prj pepextractor.prj

work "f:\vhdlproject\vhdl0716\narrow_wide_pulse_generate.vhd"
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log coregen.log

# Xilinx CORE Generator 6.1i # User = gaolig Initializing default project... Loading plug-ins... All runtime messages will be recorded in H:\file\通信ASIC课程设计\fen\coregen.log # busformat=BusFormatA
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dat bookinfo.dat

[General Information] 书名=VHDL语言程序设计及应用 作者= 页数=391 SS号=10495248 出版日期=
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ref hdpdeps.ref

V2 3 FL "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" 2006/03/17.10:34:38 H.38 EN work/DIAL1 1142562892 FL "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" \ PB ieee/STD_LOGI
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lst netlist.lst

E:\temp\sp3-U\UE Basic Board\VHDL\Dial\dial1.ngc 1142562900 OK
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