coregen.log

VHDL设计的数字时钟

# Xilinx CORE Generator 6.3.03i
# User = 王毅诚
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\Xilinx\bin\200404015010成功\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=D:\Xilinx\bin\200404015010成功
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=D:\Xilinx\bin\200404015010成功
SETPROJECT .
Set current Project to D:\Xilinx\bin\200404015010成功
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1545
XIPCPJSENDCORES spartan3