56_prefetch.vhd

北京里工大学ASIC设计研究所的100个 VHDL程序设计例子

--**VHDL*************************************************************
--
-- SRC-MODULE : PREFETCH 
-- NAME       : prefetch.vhdl
-- VERSION    : 1.0
--
-- PURPOSE    : Architecture of PREFETCH benchmark
--
-- AUTHOR     : Yan.Zongfu
-- LAST UPDATE: Mon Dec 11 11:07 1995
--
--*******************************************************************
--
-- the VHDL description of instruction fetch unit for a microprocessor
--

package types is
   subtype short is integer range 0 to 255;
end types;
use work.types.all;

-- the VHDL description for prefetch

entity prefetch is
    port (branchpc : in  short;
          ibus     : in  short;
          branch   : in  bit;
          ire      : in  bit;
          ppc      : out short;
          popc     : out short;
          obus     : out short);
end prefetch; 

--The architecture body of the prefetch entity declaration

architecture behavioral of prefetch is
begin                                
    process
        variable pc    : short;
        variable oldpc : short;
        begin  
            ppc  <= pc;
            popc <= oldpc;
            obus <= ibus + 4;
            if (branch='1') then
                pc := branchpc;
            end if;
            wait until (ire = '1');
            oldpc := pc;
            pc    := pc + 4;
    end process;
end behavioral;