代码搜索结果

vhdl work "MUSIC.vhd" vhdl work "tune.vhd" vhdl work "SPEAKER.vhd" vhdl work "NoteTabs.vhd" vhdl work "TOP .vhd"

vhdl work "SPEAKER.vhd"

vhdl work "G:\ISE9.1\menling\SPEAKER.vhd"

vhdl work "G:\ISE9.1\menling\tune.vhd"

注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化

vhdl work "vgasig.vhd"

#---------------------------------------------------------- # Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2 # for the book: Digital Signal Processing with FPGAs # Author-EMAIL: Uwe.Mey

-- ProjNav VHDL simulation template: test.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

Release 10.1 - xst K.31 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to C:/VHDL/MUP/xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU

xst -ise "C:/VHDL/MUP/MUP.ise" -intstyle ise -ifn "C:/VHDL/MUP/MUPSOURCE.xst" -ofn "C:/VHDL/MUP/MUPSOURCE.syr"