代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
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qmsg dds_vhdl.asm.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
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qrpt dds_vhdl_cmp.qrpt
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qrpt dds_vhdl_sim.qrpt
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cdb dds_vhdl.sgdiff.cdb
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qmsg dds_vhdl.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
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hier_info dds_vhdl.hier_info
|dds_vhdl
clk => pll1:u6.inclk0
suoding adder32b:u1.a[7]
fword[2] => adder32b:u1.a[8]
fword[3] => adder32b:u1.a
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rpt dds_vhdl.asm.rpt
Assembler report for dds_vhdl
Wed Nov 22 19:38:14 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
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summary dds_vhdl.fit.summary
Fitter Status : Successful - Wed Nov 22 19:38:07 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : dds_vhdl
Family : Cyclone
Devi
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rpt dds_vhdl.flow.rpt
Flow report for dds_vhdl
Wed Nov 22 19:38:19 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. F
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eqn dds_vhdl.map.eqn
--Y1__locked is pll1:u6|altpll:altpll_component|_locked
Y1__locked = PLL.LOCKED(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk),