dds_vhdl.hier_info

基于fpga的正弦波发生器设计

|dds_vhdl
clk => pll1:u6.inclk0
suoding <= pll1:u6.locked
as <= and2ab:u7.clock0
fword[0] => adder32b:u1.a[6]
fword[1] => adder32b:u1.a[7]
fword[2] => adder32b:u1.a[8]
fword[3] => adder32b:u1.a[9]
fword[4] => adder32b:u1.a[10]
fword[5] => adder32b:u1.a[11]
fword[6] => adder32b:u1.a[12]
fword[7] => adder32b:u1.a[13]
fword[8] => adder32b:u1.a[14]
fword[9] => adder32b:u1.a[15]
fword[10] => adder32b:u1.a[16]
fword[11] => adder32b:u1.a[17]
fword[12] => adder32b:u1.a[18]
fword[13] => adder32b:u1.a[19]
fword[14] => adder32b:u1.a[20]
fword[15] => adder32b:u1.a[21]
pword[0] => adder10b:u4.a[0]
pword[1] => adder10b:u4.a[1]
pword[2] => adder10b:u4.a[2]
pword[3] => adder10b:u4.a[3]
pword[4] => adder10b:u4.a[4]
pword[5] => adder10b:u4.a[5]
pword[6] => adder10b:u4.a[6]
pword[7] => adder10b:u4.a[7]
fout[0] <= sin_rom:u3.q[0]
fout[1] <= sin_rom:u3.q[1]
fout[2] <= sin_rom:u3.q[2]
fout[3] <= sin_rom:u3.q[3]
fout[4] <= sin_rom:u3.q[4]
fout[5] <= sin_rom:u3.q[5]
fout[6] <= sin_rom:u3.q[6]
fout[7] <= sin_rom:u3.q[7]
fout[8] <= sin_rom:u3.q[8]
fout[9] <= sin_rom:u3.q[9]


|dds_vhdl|adder32b:u1
a[0] => Add0.IN32
a[1] => Add0.IN31
a[2] => Add0.IN30
a[3] => Add0.IN29
a[4] => Add0.IN28
a[5] => Add0.IN27
a[6] => Add0.IN26
a[7] => Add0.IN25
a[8] => Add0.IN24
a[9] => Add0.IN23
a[10] => Add0.IN22
a[11] => Add0.IN21
a[12] => Add0.IN20
a[13] => Add0.IN19
a[14] => Add0.IN18
a[15] => Add0.IN17
a[16] => Add0.IN16
a[17] => Add0.IN15
a[18] => Add0.IN14
a[19] => Add0.IN13
a[20] => Add0.IN12
a[21] => Add0.IN11
a[22] => Add0.IN10
a[23] => Add0.IN9
a[24] => Add0.IN8
a[25] => Add0.IN7
a[26] => Add0.IN6
a[27] => Add0.IN5
a[28] => Add0.IN4
a[29] => Add0.IN3
a[30] => Add0.IN2
a[31] => Add0.IN1
b[0] => Add0.IN64
b[1] => Add0.IN63
b[2] => Add0.IN62
b[3] => Add0.IN61
b[4] => Add0.IN60
b[5] => Add0.IN59
b[6] => Add0.IN58
b[7] => Add0.IN57
b[8] => Add0.IN56
b[9] => Add0.IN55
b[10] => Add0.IN54
b[11] => Add0.IN53
b[12] => Add0.IN52
b[13] => Add0.IN51
b[14] => Add0.IN50
b[15] => Add0.IN49
b[16] => Add0.IN48
b[17] => Add0.IN47
b[18] => Add0.IN46
b[19] => Add0.IN45
b[20] => Add0.IN44
b[21] => Add0.IN43
b[22] => Add0.IN42
b[23] => Add0.IN41
b[24] => Add0.IN40
b[25] => Add0.IN39
b[26] => Add0.IN38
b[27] => Add0.IN37
b[28] => Add0.IN36
b[29] => Add0.IN35
b[30] => Add0.IN34
b[31] => Add0.IN33
s[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|reg32b:u2
load => dout[0]~reg0.CLK
load => dout[1]~reg0.CLK
load => dout[2]~reg0.CLK
load => dout[3]~reg0.CLK
load => dout[4]~reg0.CLK
load => dout[5]~reg0.CLK
load => dout[6]~reg0.CLK
load => dout[7]~reg0.CLK
load => dout[8]~reg0.CLK
load => dout[9]~reg0.CLK
load => dout[10]~reg0.CLK
load => dout[11]~reg0.CLK
load => dout[12]~reg0.CLK
load => dout[13]~reg0.CLK
load => dout[14]~reg0.CLK
load => dout[15]~reg0.CLK
load => dout[16]~reg0.CLK
load => dout[17]~reg0.CLK
load => dout[18]~reg0.CLK
load => dout[19]~reg0.CLK
load => dout[20]~reg0.CLK
load => dout[21]~reg0.CLK
load => dout[22]~reg0.CLK
load => dout[23]~reg0.CLK
load => dout[24]~reg0.CLK
load => dout[25]~reg0.CLK
load => dout[26]~reg0.CLK
load => dout[27]~reg0.CLK
load => dout[28]~reg0.CLK
load => dout[29]~reg0.CLK
load => dout[30]~reg0.CLK
load => dout[31]~reg0.CLK
rst32 => dout[0]~reg0.ACLR
rst32 => dout[1]~reg0.ACLR
rst32 => dout[2]~reg0.ACLR
rst32 => dout[3]~reg0.ACLR
rst32 => dout[4]~reg0.ACLR
rst32 => dout[5]~reg0.ACLR
rst32 => dout[6]~reg0.ACLR
rst32 => dout[7]~reg0.ACLR
rst32 => dout[8]~reg0.ACLR
rst32 => dout[9]~reg0.ACLR
rst32 => dout[10]~reg0.ACLR
rst32 => dout[11]~reg0.ACLR
rst32 => dout[12]~reg0.ACLR
rst32 => dout[13]~reg0.ACLR
rst32 => dout[14]~reg0.ACLR
rst32 => dout[15]~reg0.ACLR
rst32 => dout[16]~reg0.ACLR
rst32 => dout[17]~reg0.ACLR
rst32 => dout[18]~reg0.ACLR
rst32 => dout[19]~reg0.ACLR
rst32 => dout[20]~reg0.ACLR
rst32 => dout[21]~reg0.ACLR
rst32 => dout[22]~reg0.ACLR
rst32 => dout[23]~reg0.ACLR
rst32 => dout[24]~reg0.ACLR
rst32 => dout[25]~reg0.ACLR
rst32 => dout[26]~reg0.ACLR
rst32 => dout[27]~reg0.ACLR
rst32 => dout[28]~reg0.ACLR
rst32 => dout[29]~reg0.ACLR
rst32 => dout[30]~reg0.ACLR
rst32 => dout[31]~reg0.ACLR
din[0] => dout[0]~reg0.DATAIN
din[1] => dout[1]~reg0.DATAIN
din[2] => dout[2]~reg0.DATAIN
din[3] => dout[3]~reg0.DATAIN
din[4] => dout[4]~reg0.DATAIN
din[5] => dout[5]~reg0.DATAIN
din[6] => dout[6]~reg0.DATAIN
din[7] => dout[7]~reg0.DATAIN
din[8] => dout[8]~reg0.DATAIN
din[9] => dout[9]~reg0.DATAIN
din[10] => dout[10]~reg0.DATAIN
din[11] => dout[11]~reg0.DATAIN
din[12] => dout[12]~reg0.DATAIN
din[13] => dout[13]~reg0.DATAIN
din[14] => dout[14]~reg0.DATAIN
din[15] => dout[15]~reg0.DATAIN
din[16] => dout[16]~reg0.DATAIN
din[17] => dout[17]~reg0.DATAIN
din[18] => dout[18]~reg0.DATAIN
din[19] => dout[19]~reg0.DATAIN
din[20] => dout[20]~reg0.DATAIN
din[21] => dout[21]~reg0.DATAIN
din[22] => dout[22]~reg0.DATAIN
din[23] => dout[23]~reg0.DATAIN
din[24] => dout[24]~reg0.DATAIN
din[25] => dout[25]~reg0.DATAIN
din[26] => dout[26]~reg0.DATAIN
din[27] => dout[27]~reg0.DATAIN
din[28] => dout[28]~reg0.DATAIN
din[29] => dout[29]~reg0.DATAIN
din[30] => dout[30]~reg0.DATAIN
din[31] => dout[31]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[16] <= dout[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[17] <= dout[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[18] <= dout[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[19] <= dout[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[20] <= dout[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[21] <= dout[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[22] <= dout[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[23] <= dout[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[24] <= dout[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[25] <= dout[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[26] <= dout[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[27] <= dout[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[28] <= dout[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[29] <= dout[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[30] <= dout[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[31] <= dout[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|sin_rom:u3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|dds_vhdl|sin_rom:u3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_o351:auto_generated.address_a[0]
address_a[1] => altsyncram_o351:auto_generated.address_a[1]
address_a[2] => altsyncram_o351:auto_generated.address_a[2]
address_a[3] => altsyncram_o351:auto_generated.address_a[3]
address_a[4] => altsyncram_o351:auto_generated.address_a[4]
address_a[5] => altsyncram_o351:auto_generated.address_a[5]
address_a[6] => altsyncram_o351:auto_generated.address_a[6]
address_a[7] => altsyncram_o351:auto_generated.address_a[7]
address_a[8] => altsyncram_o351:auto_generated.address_a[8]
address_a[9] => altsyncram_o351:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~