dds_vhdl.map.eqn

基于fpga的正弦波发生器设计

--Y1__locked is pll1:u6|altpll:altpll_component|_locked
Y1__locked = PLL.LOCKED(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--Y1__clk0 is pll1:u6|altpll:altpll_component|_clk0
Y1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--J1_clock0 is and2ab:u7|clock0
--operation mode is normal

J1_clock0 = Y1__locked & Y1__clk0;


--T1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[9]_PORT_A_data_in = VCC;
T1_q_a[9]_PORT_A_data_in_reg = DFFE(T1_q_a[9]_PORT_A_data_in, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_data_in = U1_ram_rom_data_reg[9];
T1_q_a[9]_PORT_B_data_in_reg = DFFE(T1_q_a[9]_PORT_B_data_in, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[9]_PORT_A_address_reg = DFFE(T1_q_a[9]_PORT_A_address, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[9]_PORT_B_address_reg = DFFE(T1_q_a[9]_PORT_B_address, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_write_enable = GND;
T1_q_a[9]_PORT_A_write_enable_reg = DFFE(T1_q_a[9]_PORT_A_write_enable, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_write_enable = U1L53;
T1_q_a[9]_PORT_B_write_enable_reg = DFFE(T1_q_a[9]_PORT_B_write_enable, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_clock_0 = J1_clock0;
T1_q_a[9]_clock_1 = A1L5;
T1_q_a[9]_PORT_A_data_out = MEMORY(T1_q_a[9]_PORT_A_data_in_reg, T1_q_a[9]_PORT_B_data_in_reg, T1_q_a[9]_PORT_A_address_reg, T1_q_a[9]_PORT_B_address_reg, T1_q_a[9]_PORT_A_write_enable_reg, T1_q_a[9]_PORT_B_write_enable_reg, , , T1_q_a[9]_clock_0, T1_q_a[9]_clock_1, , , , );
T1_q_a[9]_PORT_A_data_out_reg = DFFE(T1_q_a[9]_PORT_A_data_out, T1_q_a[9]_clock_0, , , );
T1_q_a[9] = T1_q_a[9]_PORT_A_data_out_reg[0];

--T1_q_b[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[9]
T1_q_b[9]_PORT_A_data_in = VCC;
T1_q_b[9]_PORT_A_data_in_reg = DFFE(T1_q_b[9]_PORT_A_data_in, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_data_in = U1_ram_rom_data_reg[9];
T1_q_b[9]_PORT_B_data_in_reg = DFFE(T1_q_b[9]_PORT_B_data_in, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[9]_PORT_A_address_reg = DFFE(T1_q_b[9]_PORT_A_address, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[9]_PORT_B_address_reg = DFFE(T1_q_b[9]_PORT_B_address, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_write_enable = GND;
T1_q_b[9]_PORT_A_write_enable_reg = DFFE(T1_q_b[9]_PORT_A_write_enable, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_write_enable = U1L53;
T1_q_b[9]_PORT_B_write_enable_reg = DFFE(T1_q_b[9]_PORT_B_write_enable, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_clock_0 = J1_clock0;
T1_q_b[9]_clock_1 = A1L5;
T1_q_b[9]_PORT_B_data_out = MEMORY(T1_q_b[9]_PORT_A_data_in_reg, T1_q_b[9]_PORT_B_data_in_reg, T1_q_b[9]_PORT_A_address_reg, T1_q_b[9]_PORT_B_address_reg, T1_q_b[9]_PORT_A_write_enable_reg, T1_q_b[9]_PORT_B_write_enable_reg, , , T1_q_b[9]_clock_0, T1_q_b[9]_clock_1, , , , );
T1_q_b[9] = T1_q_b[9]_PORT_B_data_out[0];


--T1_q_a[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[8]_PORT_A_data_in = VCC;
T1_q_a[8]_PORT_A_data_in_reg = DFFE(T1_q_a[8]_PORT_A_data_in, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_data_in = U1_ram_rom_data_reg[8];
T1_q_a[8]_PORT_B_data_in_reg = DFFE(T1_q_a[8]_PORT_B_data_in, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[8]_PORT_A_address_reg = DFFE(T1_q_a[8]_PORT_A_address, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[8]_PORT_B_address_reg = DFFE(T1_q_a[8]_PORT_B_address, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_write_enable = GND;
T1_q_a[8]_PORT_A_write_enable_reg = DFFE(T1_q_a[8]_PORT_A_write_enable, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_write_enable = U1L53;
T1_q_a[8]_PORT_B_write_enable_reg = DFFE(T1_q_a[8]_PORT_B_write_enable, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_clock_0 = J1_clock0;
T1_q_a[8]_clock_1 = A1L5;
T1_q_a[8]_PORT_A_data_out = MEMORY(T1_q_a[8]_PORT_A_data_in_reg, T1_q_a[8]_PORT_B_data_in_reg, T1_q_a[8]_PORT_A_address_reg, T1_q_a[8]_PORT_B_address_reg, T1_q_a[8]_PORT_A_write_enable_reg, T1_q_a[8]_PORT_B_write_enable_reg, , , T1_q_a[8]_clock_0, T1_q_a[8]_clock_1, , , , );
T1_q_a[8]_PORT_A_data_out_reg = DFFE(T1_q_a[8]_PORT_A_data_out, T1_q_a[8]_clock_0, , , );
T1_q_a[8] = T1_q_a[8]_PORT_A_data_out_reg[0];

--T1_q_b[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[8]
T1_q_b[8]_PORT_A_data_in = VCC;
T1_q_b[8]_PORT_A_data_in_reg = DFFE(T1_q_b[8]_PORT_A_data_in, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_data_in = U1_ram_rom_data_reg[8];
T1_q_b[8]_PORT_B_data_in_reg = DFFE(T1_q_b[8]_PORT_B_data_in, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[8]_PORT_A_address_reg = DFFE(T1_q_b[8]_PORT_A_address, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[8]_PORT_B_address_reg = DFFE(T1_q_b[8]_PORT_B_address, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_write_enable = GND;
T1_q_b[8]_PORT_A_write_enable_reg = DFFE(T1_q_b[8]_PORT_A_write_enable, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_write_enable = U1L53;
T1_q_b[8]_PORT_B_write_enable_reg = DFFE(T1_q_b[8]_PORT_B_write_enable, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_clock_0 = J1_clock0;
T1_q_b[8]_clock_1 = A1L5;
T1_q_b[8]_PORT_B_data_out = MEMORY(T1_q_b[8]_PORT_A_data_in_reg, T1_q_b[8]_PORT_B_data_in_reg, T1_q_b[8]_PORT_A_address_reg, T1_q_b[8]_PORT_B_address_reg, T1_q_b[8]_PORT_A_write_enable_reg, T1_q_b[8]_PORT_B_write_enable_reg, , , T1_q_b[8]_clock_0, T1_q_b[8]_clock_1, , , , );
T1_q_b[8] = T1_q_b[8]_PORT_B_data_out[0];


--T1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[7]_PORT_A_data_in = VCC;
T1_q_a[7]_PORT_A_data_in_reg = DFFE(T1_q_a[7]_PORT_A_data_in, T1_q_a[7]_clock_0, , , );
T1_q_a[7]_PORT_B_data_in = U1_ram_rom_data_reg[7];
T1_q_a[7]_PORT_B_data_in_reg = DFFE(T1_q_a[7]_PORT_B_data_in, T1_q_a[7]_clock_1, , , );
T1_q_a[7]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[7]_PORT_A_address_reg = DFFE(T1_q_a[7]_PORT_A_address, T1_q_a[7]_clock_0, , , );
T1_q_a[7]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[7]_PORT_B_address_reg = DFFE(T1_q_a[7]_PORT_B_address, T1_q_a[7]_clock_1, , , );
T1_q_a[7]_PORT_A_write_enable = GND;
T1_q_a[7]_PORT_A_write_enable_reg = DFFE(T1_q_a[7]_PORT_A_write_enable, T1_q_a[7]_clock_0, , , );
T1_q_a[7]_PORT_B_write_enable = U1L53;
T1_q_a[7]_PORT_B_write_enable_reg = DFFE(T1_q_a[7]_PORT_B_write_enable, T1_q_a[7]_clock_1, , , );
T1_q_a[7]_clock_0 = J1_clock0;
T1_q_a[7]_clock_1 = A1L5;
T1_q_a[7]_PORT_A_data_out = MEMORY(T1_q_a[7]_PORT_A_data_in_reg, T1_q_a[7]_PORT_B_data_in_reg, T1_q_a[7]_PORT_A_address_reg, T1_q_a[7]_PORT_B_address_reg, T1_q_a[7]_PORT_A_write_enable_reg, T1_q_a[7]_PORT_B_write_enable_reg, , , T1_q_a[7]_clock_0, T1_q_a[7]_clock_1, , , , );
T1_q_a[7]_PORT_A_data_out_reg = DFFE(T1_q_a[7]_PORT_A_data_out, T1_q_a[7]_clock_0, , , );
T1_q_a[7] = T1_q_a[7]_PORT_A_data_out_reg[0];

--T1_q_b[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[7]
T1_q_b[7]_PORT_A_data_in = VCC;
T1_q_b[7]_PORT_A_data_in_reg = DFFE(T1_q_b[7]_PORT_A_data_in, T1_q_b[7]_clock_0, , , );
T1_q_b[7]_PORT_B_data_in = U1_ram_rom_data_reg[7];
T1_q_b[7]_PORT_B_data_in_reg = DFFE(T1_q_b[7]_PORT_B_data_in, T1_q_b[7]_clock_1, , , );
T1_q_b[7]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[7]_PORT_A_address_reg = DFFE(T1_q_b[7]_PORT_A_address, T1_q_b[7]_clock_0, , , );
T1_q_b[7]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[7]_PORT_B_address_reg = DFFE(T1_q_b[7]_PORT_B_address, T1_q_b[7]_clock_1, , , );
T1_q_b[7]_PORT_A_write_enable = GND;
T1_q_b[7]_PORT_A_write_enable_reg = DFFE(T1_q_b[7]_PORT_A_write_enable, T1_q_b[7]_clock_0, , , );
T1_q_b[7]_PORT_B_write_enable = U1L53;
T1_q_b[7]_PORT_B_write_enable_reg = DFFE(T1_q_b[7]_PORT_B_write_enable, T1_q_b[7]_clock_1, , , );
T1_q_b[7]_clock_0 = J1_clock0;
T1_q_b[7]_clock_1 = A1L5;
T1_q_b[7]_PORT_B_data_out = MEMORY(T1_q_b[7]_PORT_A_data_in_reg, T1_q_b[7]_PORT_B_data_in_reg, T1_q_b[7]_PORT_A_address_reg, T1_q_b[7]_PORT_B_address_reg, T1_q_b[7]_PORT_A_write_enable_reg, T1_q_b[7]_PORT_B_write_enable_reg, , , T1_q_b[7]_clock_0, T1_q_b[7]_clock_1, , , , );
T1_q_b[7] = T1_q_b[7]_PORT_B_data_out[0];


--T1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[6]_PORT_A_data_in = VCC;
T1_q_a[6]_PORT_A_data_in_reg = DFFE(T1_q_a[6]_PORT_A_data_in, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_data_in = U1_ram_rom_data_reg[6];
T1_q_a[6]_PORT_B_data_in_reg = DFFE(T1_q_a[6]_PORT_B_data_in, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[6]_PORT_A_address_reg = DFFE(T1_q_a[6]_PORT_A_address, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[6]_PORT_B_address_reg = DFFE(T1_q_a[6]_PORT_B_address, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_PORT_A_write_enable = GND;
T1_q_a[6]_PORT_A_write_enable_reg = DFFE(T1_q_a[6]_PORT_A_write_enable, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_write_enable = U1L53;
T1_q_a[6]_PORT_B_write_enable_reg = DFFE(T1_q_a[6]_PORT_B_write_enable, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_clock_0 = J1_clock0;
T1_q_a[6]_clock_1 = A1L5;
T1_q_a[6]_PORT_A_data_out = MEMORY(T1_q_a[6]_PORT_A_data_in_reg, T1_q_a[6]_PORT_B_data_in_reg, T1_q_a[6]_PORT_A_address_reg, T1_q_a[6]_PORT_B_address_reg, T1_q_a[6]_PORT_A_write_enable_reg, T1_q_a[6]_PORT_B_write_enable_reg, , , T1_q_a[6]_clock_0, T1_q_a[6]_clock_1, , , , );
T1_q_a[6]_PORT_A_data_out_reg = DFFE(T1_q_a[6]_PORT_A_data_out, T1_q_a[6]_clock_0, , , );
T1_q_a[6] = T1_q_a[6]_PORT_A_data_out_reg[0];

--T1_q_b[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[6]
T1_q_b[6]_PORT_A_data_in = VCC;
T1_q_b[6]_PORT_A_data_in_reg = DFFE(T1_q_b[6]_PORT_A_data_in, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_data_in = U1_ram_rom_data_reg[6];
T1_q_b[6]_PORT_B_data_in_reg = DFFE(T1_q_b[6]_PORT_B_data_in, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[6]_PORT_A_address_reg = DFFE(T1_q_b[6]_PORT_A_address, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[6]_PORT_B_address_reg = DFFE(T1_q_b[6]_PORT_B_address, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_PORT_A_write_enable = GND;
T1_q_b[6]_PORT_A_write_enable_reg = DFFE(T1_q_b[6]_PORT_A_write_enable, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_write_enable = U1L53;
T1_q_b[6]_PORT_B_write_enable_reg = DFFE(T1_q_b[6]_PORT_B_write_enable, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_clock_0 = J1_clock0;
T1_q_b[6]_clock_1 = A1L5;
T1_q_b[6]_PORT_B_data_out = MEMORY(T1_q_b[6]_PORT_A_data_in_reg, T1_q_b[6]_PORT_B_data_in_reg, T1_q_b[6]_PORT_A_address_reg, T1_q_b[6]_PORT_B_address_reg, T1_q_b[6]_PORT_A_write_enable_reg, T1_q_b[6]_PORT_B_write_enable_reg, , , T1_q_b[6]_clock_0, T1_q_b[6]_clock_1, , , , );
T1_q_b[6] = T1_q_b[6]_PORT_B_data_out[0];


--T1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[5]_PORT_A_data_in = VCC;
T1_q_a[5]_PORT_A_data_in_reg = DFFE(T1_q_a[5]_PORT_A_data_in, T1_q_a[5]_clock_0, , , );
T1_q_a[5]_PORT_B_data_in = U1_ram_rom_data_reg[5];
T1_q_a[5]_PORT_B_data_in_reg = DFFE(T1_q_a[5]_PORT_B_data_in, T1_q_a[5]_clock_1, , , );
T1_q_a[5]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[5]_PORT_A_address_reg = DFFE(T1_q_a[5]_PORT_A_address, T1_q_a[5]_clock_0, , , );
T1_q_a[5]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[5]_PORT_B_address_reg = DFFE(T1_q_a[5]_PORT_B_address, T1_q_a[5]_clock_1, , , );
T1_q_a[5]_PORT_A_write_enable = GND;
T1_q_a[5]_PORT_A_write_enable_reg = DFFE(T1_q_a[5]_PORT_A_write_enable, T1_q_a[5]_clock_0, , , );
T1_q_a[5]_PORT_B_write_enable = U1L53;
T1_q_a[5]_PORT_B_write_enable_reg = DFFE(T1_q_a[5]_PORT_B_write_enable, T1_q_a[5]_clock_1, , , );
T1_q_a[5]_clock_0 = J1_clock0;
T1_q_a[5]_clock_1 = A1L5;
T1_q_a[5]_PORT_A_data_out = MEMORY(T1_q_a[5]_PORT_A_data_in_reg, T1_q_a[5]_PORT_B_data_in_reg, T1_q_a[5]_PORT_A_address_reg, T1_q_a[5]_PORT_B_address_reg, T1_q_a[5]_PORT_A_write_enable_reg, T1_q_a[5]_PORT_B_write_enable_reg, , , T1_q_a[5]_clock_0, T1_q_a[5]_clock_1, , , , );
T1_q_a[5]_PORT_A_data_out_reg = DFFE(T1_q_a[5]_PORT_A_data_out, T1_q_a[5]_clock_0, , , );
T1_q_a[5] = T1_q_a[5]_PORT_A_data_out_reg[0];

--T1_q_b[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[5]
T1_q_b[5]_PORT_A_data_in = VCC;
T1_q_b[5]_PORT_A_data_in_reg = DFFE(T1_q_b[5]_PORT_A_data_in, T1_q_b[5]_clock_0, , , );
T1_q_b[5]_PORT_B_data_in = U1_ram_rom_data_reg[5];
T1_q_b[5]_PORT_B_data_in_reg = DFFE(T1_q_b[5]_PORT_B_data_in, T1_q_b[5]_clock_1, , , );
T1_q_b[5]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[5]_PORT_A_address_reg = DFFE(T1_q_b[5]_PORT_A_address, T1_q_b[5]_clock_0, , , );
T1_q_b[5]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[5]_PORT_B_address_reg = DFFE(T1_q_b[5]_PORT_B_address, T1_q_b[5]_clock_1, , , );
T1_q_b[5]_PORT_A_write_enable = GND;
T1_q_b[5]_PORT_A_write_enable_reg = DFFE(T1_q_b[5]_PORT_A_write_enable, T1_q_b[5]_clock_0, , , );
T1_q_b[5]_PORT_B_write_enable = U1L53;
T1_q_b[5]_PORT_B_write_enable_reg = DFFE(T1_q_b[5]_PORT_B_write_enable, T1_q_b[5]_clock_1, , , );
T1_q_b[5]_clock_0 = J1_clock0;
T1_q_b[5]_clock_1 = A1L5;
T1_q_b[5]_PORT_B_data_out = MEMORY(T1_q_b[5]_PORT_A_data_in_reg, T1_q_b[5]_PORT_B_data_in_reg, T1_q_b[5]_PORT_A_address_reg, T1_q_b[5]_PORT_B_address_reg, T1_q_b[5]_PORT_A_write_enable_reg, T1_q_b[5]_PORT_B_write_enable_reg, , , T1_q_b[5]_clock_0, T1_q_b[5]_clock_1, , , , );
T1_q_b[5] = T1_q_b[5]_PORT_B_data_out[0];


--T1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[4]_PORT_A_data_in = VCC;
T1_q_a[4]_PORT_A_data_in_reg = DFFE(T1_q_a[4]_PORT_A_data_in, T1_q_a[4]_clock_0, , , );
T1_q_a[4]_PORT_B_data_in = U1_ram_rom_data_reg[4];
T1_q_a[4]_PORT_B_data_in_reg = DFFE(T1_q_a[4]_PORT_B_data_in, T1_q_a[4]_clock_1, , , );
T1_q_a[4]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[4]_PORT_A_address_reg = DFFE(T1_q_a[4]_PORT_A_address, T1_q_a[4]_clock_0, , , );
T1_q_a[4]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[4]_PORT_B_address_reg = DFFE(T1_q_a[4]_PORT_B_address, T1_q_a[4]_clock_1, , , );
T1_q_a[4]_PORT_A_write_enable = GND;
T1_q_a[4]_PORT_A_write_enable_reg = DFFE(T1_q_a[4]_PORT_A_write_enable, T1_q_a[4]_clock_0, , , );
T1_q_a[4]_PORT_B_write_enable = U1L53;
T1_q_a[4]_PORT_B_write_enable_reg = DFFE(T1_q_a[4]_PORT_B_write_enable, T1_q_a[4]_clock_1, , , );
T1_q_a[4]_clock_0 = J1_clock0;
T1_q_a[4]_clock_1 = A1L5;
T1_q_a[4]_PORT_A_data_out = MEMORY(T1_q_a[4]_PORT_A_data_in_reg, T1_q_a[4]_PORT_B_data_in_reg, T1_q_a[4]_PORT_A_address_reg, T1_q_a[4]_PORT_B_address_reg, T1_q_a[4]_PORT_A_write_enable_reg, T1_q_a[4]_PORT_B_write_enable_reg, , , T1_q_a[4]_clock_0, T1_q_a[4]_clock_1, , , , );
T1_q_a[4]_PORT_A_data_out_reg = DFFE(T1_q_a[4]_PORT_A_data_out, T1_q_a[4]_clock_0, , , );
T1_q_a[4] = T1_q_a[4]_PORT_A_data_out_reg[0];