代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
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www.eeworm.com/read/195920/8122957
hier_info dds_vhdl.hier_info
|DDS_VHDL
CLK => sin_rom:u6.inclock
CLK => reg10b:u5.Load
CLK => sin_rom:u3.inclock
CLK => reg32b:u2.Load
CLK => CLK_DA.DATAIN
CLK_DA adder32b:u1.A[20
www.eeworm.com/read/195920/8122980
rpt dds_vhdl.asm.rpt
Assembler report for dds_vhdl
Wed Dec 14 16:07:30 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
www.eeworm.com/read/195920/8122983
summary dds_vhdl.fit.summary
Flow Status : Successful - Wed Dec 14 16:07:26 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : DDS_VHDL
Family : Cyclone
Device
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rpt dds_vhdl.flow.rpt
Flow report for dds_vhdl
Wed Dec 14 16:07:34 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. F
www.eeworm.com/read/195920/8122999
eqn dds_vhdl.map.eqn
--RB1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Wi
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zip sdr-sdram-vhdl.zip
www.eeworm.com/read/146230/12662909
txt 流水灯vhdl程序.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity line is
port(
clk:in std_logic;
clk1:in std_logic;
rst:in std_logic;
start_flag:in st
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pdf vhdl语言例程集锦.pdf
www.eeworm.com/read/142631/12935101
mht 问“vhdl”的问题.mht
From:
Subject: =?gb2312?B?tbG1scLbzLMgLSA6OrzGy+O7+ry8yvU6OiAtILHgs8zM7LXYIC0g?=
=?gb2312?B?zsqhsFZIREyhsbXEzsrM4qOho6EgLSBwb3dlcmVkIGJ5IHh0aGFua3M=?=
Date: Sa
www.eeworm.com/read/327446/13077958