dds_vhdl.map.eqn

数字移相信号发生器设计

--RB1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[9]_PORT_A_data_in = VCC;
RB1_q_a[9]_PORT_A_data_in_reg = DFFE(RB1_q_a[9]_PORT_A_data_in, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_data_in = SB1_ram_rom_data_reg[9];
RB1_q_a[9]_PORT_B_data_in_reg = DFFE(RB1_q_a[9]_PORT_B_data_in, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[9]_PORT_A_address_reg = DFFE(RB1_q_a[9]_PORT_A_address, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[9]_PORT_B_address_reg = DFFE(RB1_q_a[9]_PORT_B_address, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_PORT_A_write_enable = GND;
RB1_q_a[9]_PORT_A_write_enable_reg = DFFE(RB1_q_a[9]_PORT_A_write_enable, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_write_enable = SB1L62;
RB1_q_a[9]_PORT_B_write_enable_reg = DFFE(RB1_q_a[9]_PORT_B_write_enable, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_clock_0 = CLK;
RB1_q_a[9]_clock_1 = A1L5;
RB1_q_a[9]_PORT_A_data_out = MEMORY(RB1_q_a[9]_PORT_A_data_in_reg, RB1_q_a[9]_PORT_B_data_in_reg, RB1_q_a[9]_PORT_A_address_reg, RB1_q_a[9]_PORT_B_address_reg, RB1_q_a[9]_PORT_A_write_enable_reg, RB1_q_a[9]_PORT_B_write_enable_reg, , , RB1_q_a[9]_clock_0, RB1_q_a[9]_clock_1, , , , );
RB1_q_a[9] = RB1_q_a[9]_PORT_A_data_out[0];

--RB1_q_b[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[9]
RB1_q_b[9]_PORT_A_data_in = VCC;
RB1_q_b[9]_PORT_A_data_in_reg = DFFE(RB1_q_b[9]_PORT_A_data_in, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_data_in = SB1_ram_rom_data_reg[9];
RB1_q_b[9]_PORT_B_data_in_reg = DFFE(RB1_q_b[9]_PORT_B_data_in, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[9]_PORT_A_address_reg = DFFE(RB1_q_b[9]_PORT_A_address, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_b[9]_PORT_B_address_reg = DFFE(RB1_q_b[9]_PORT_B_address, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_PORT_A_write_enable = GND;
RB1_q_b[9]_PORT_A_write_enable_reg = DFFE(RB1_q_b[9]_PORT_A_write_enable, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_write_enable = SB1L62;
RB1_q_b[9]_PORT_B_write_enable_reg = DFFE(RB1_q_b[9]_PORT_B_write_enable, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_clock_0 = CLK;
RB1_q_b[9]_clock_1 = A1L5;
RB1_q_b[9]_PORT_B_data_out = MEMORY(RB1_q_b[9]_PORT_A_data_in_reg, RB1_q_b[9]_PORT_B_data_in_reg, RB1_q_b[9]_PORT_A_address_reg, RB1_q_b[9]_PORT_B_address_reg, RB1_q_b[9]_PORT_A_write_enable_reg, RB1_q_b[9]_PORT_B_write_enable_reg, , , RB1_q_b[9]_clock_0, RB1_q_b[9]_clock_1, , , , );
RB1_q_b[9] = RB1_q_b[9]_PORT_B_data_out[0];


--RB1_q_a[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[8]_PORT_A_data_in = VCC;
RB1_q_a[8]_PORT_A_data_in_reg = DFFE(RB1_q_a[8]_PORT_A_data_in, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_data_in = SB1_ram_rom_data_reg[8];
RB1_q_a[8]_PORT_B_data_in_reg = DFFE(RB1_q_a[8]_PORT_B_data_in, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[8]_PORT_A_address_reg = DFFE(RB1_q_a[8]_PORT_A_address, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[8]_PORT_B_address_reg = DFFE(RB1_q_a[8]_PORT_B_address, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_PORT_A_write_enable = GND;
RB1_q_a[8]_PORT_A_write_enable_reg = DFFE(RB1_q_a[8]_PORT_A_write_enable, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_write_enable = SB1L62;
RB1_q_a[8]_PORT_B_write_enable_reg = DFFE(RB1_q_a[8]_PORT_B_write_enable, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_clock_0 = CLK;
RB1_q_a[8]_clock_1 = A1L5;
RB1_q_a[8]_PORT_A_data_out = MEMORY(RB1_q_a[8]_PORT_A_data_in_reg, RB1_q_a[8]_PORT_B_data_in_reg, RB1_q_a[8]_PORT_A_address_reg, RB1_q_a[8]_PORT_B_address_reg, RB1_q_a[8]_PORT_A_write_enable_reg, RB1_q_a[8]_PORT_B_write_enable_reg, , , RB1_q_a[8]_clock_0, RB1_q_a[8]_clock_1, , , , );
RB1_q_a[8] = RB1_q_a[8]_PORT_A_data_out[0];

--RB1_q_b[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[8]
RB1_q_b[8]_PORT_A_data_in = VCC;
RB1_q_b[8]_PORT_A_data_in_reg = DFFE(RB1_q_b[8]_PORT_A_data_in, RB1_q_b[8]_clock_0, , , );
RB1_q_b[8]_PORT_B_data_in = SB1_ram_rom_data_reg[8];
RB1_q_b[8]_PORT_B_data_in_reg = DFFE(RB1_q_b[8]_PORT_B_data_in, RB1_q_b[8]_clock_1, , , );
RB1_q_b[8]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[8]_PORT_A_address_reg = DFFE(RB1_q_b[8]_PORT_A_address, RB1_q_b[8]_clock_0, , , );
RB1_q_b[8]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_b[8]_PORT_B_address_reg = DFFE(RB1_q_b[8]_PORT_B_address, RB1_q_b[8]_clock_1, , , );
RB1_q_b[8]_PORT_A_write_enable = GND;
RB1_q_b[8]_PORT_A_write_enable_reg = DFFE(RB1_q_b[8]_PORT_A_write_enable, RB1_q_b[8]_clock_0, , , );
RB1_q_b[8]_PORT_B_write_enable = SB1L62;
RB1_q_b[8]_PORT_B_write_enable_reg = DFFE(RB1_q_b[8]_PORT_B_write_enable, RB1_q_b[8]_clock_1, , , );
RB1_q_b[8]_clock_0 = CLK;
RB1_q_b[8]_clock_1 = A1L5;
RB1_q_b[8]_PORT_B_data_out = MEMORY(RB1_q_b[8]_PORT_A_data_in_reg, RB1_q_b[8]_PORT_B_data_in_reg, RB1_q_b[8]_PORT_A_address_reg, RB1_q_b[8]_PORT_B_address_reg, RB1_q_b[8]_PORT_A_write_enable_reg, RB1_q_b[8]_PORT_B_write_enable_reg, , , RB1_q_b[8]_clock_0, RB1_q_b[8]_clock_1, , , , );
RB1_q_b[8] = RB1_q_b[8]_PORT_B_data_out[0];


--RB1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[7]_PORT_A_data_in = VCC;
RB1_q_a[7]_PORT_A_data_in_reg = DFFE(RB1_q_a[7]_PORT_A_data_in, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7]_PORT_B_data_in = SB1_ram_rom_data_reg[7];
RB1_q_a[7]_PORT_B_data_in_reg = DFFE(RB1_q_a[7]_PORT_B_data_in, RB1_q_a[7]_clock_1, , , );
RB1_q_a[7]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[7]_PORT_A_address_reg = DFFE(RB1_q_a[7]_PORT_A_address, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[7]_PORT_B_address_reg = DFFE(RB1_q_a[7]_PORT_B_address, RB1_q_a[7]_clock_1, , , );
RB1_q_a[7]_PORT_A_write_enable = GND;
RB1_q_a[7]_PORT_A_write_enable_reg = DFFE(RB1_q_a[7]_PORT_A_write_enable, RB1_q_a[7]_clock_0, , , );
RB1_q_a[7]_PORT_B_write_enable = SB1L62;
RB1_q_a[7]_PORT_B_write_enable_reg = DFFE(RB1_q_a[7]_PORT_B_write_enable, RB1_q_a[7]_clock_1, , , );
RB1_q_a[7]_clock_0 = CLK;
RB1_q_a[7]_clock_1 = A1L5;
RB1_q_a[7]_PORT_A_data_out = MEMORY(RB1_q_a[7]_PORT_A_data_in_reg, RB1_q_a[7]_PORT_B_data_in_reg, RB1_q_a[7]_PORT_A_address_reg, RB1_q_a[7]_PORT_B_address_reg, RB1_q_a[7]_PORT_A_write_enable_reg, RB1_q_a[7]_PORT_B_write_enable_reg, , , RB1_q_a[7]_clock_0, RB1_q_a[7]_clock_1, , , , );
RB1_q_a[7] = RB1_q_a[7]_PORT_A_data_out[0];

--RB1_q_b[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[7]
RB1_q_b[7]_PORT_A_data_in = VCC;
RB1_q_b[7]_PORT_A_data_in_reg = DFFE(RB1_q_b[7]_PORT_A_data_in, RB1_q_b[7]_clock_0, , , );
RB1_q_b[7]_PORT_B_data_in = SB1_ram_rom_data_reg[7];
RB1_q_b[7]_PORT_B_data_in_reg = DFFE(RB1_q_b[7]_PORT_B_data_in, RB1_q_b[7]_clock_1, , , );
RB1_q_b[7]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[7]_PORT_A_address_reg = DFFE(RB1_q_b[7]_PORT_A_address, RB1_q_b[7]_clock_0, , , );
RB1_q_b[7]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_b[7]_PORT_B_address_reg = DFFE(RB1_q_b[7]_PORT_B_address, RB1_q_b[7]_clock_1, , , );
RB1_q_b[7]_PORT_A_write_enable = GND;
RB1_q_b[7]_PORT_A_write_enable_reg = DFFE(RB1_q_b[7]_PORT_A_write_enable, RB1_q_b[7]_clock_0, , , );
RB1_q_b[7]_PORT_B_write_enable = SB1L62;
RB1_q_b[7]_PORT_B_write_enable_reg = DFFE(RB1_q_b[7]_PORT_B_write_enable, RB1_q_b[7]_clock_1, , , );
RB1_q_b[7]_clock_0 = CLK;
RB1_q_b[7]_clock_1 = A1L5;
RB1_q_b[7]_PORT_B_data_out = MEMORY(RB1_q_b[7]_PORT_A_data_in_reg, RB1_q_b[7]_PORT_B_data_in_reg, RB1_q_b[7]_PORT_A_address_reg, RB1_q_b[7]_PORT_B_address_reg, RB1_q_b[7]_PORT_A_write_enable_reg, RB1_q_b[7]_PORT_B_write_enable_reg, , , RB1_q_b[7]_clock_0, RB1_q_b[7]_clock_1, , , , );
RB1_q_b[7] = RB1_q_b[7]_PORT_B_data_out[0];


--RB1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[6]_PORT_A_data_in = VCC;
RB1_q_a[6]_PORT_A_data_in_reg = DFFE(RB1_q_a[6]_PORT_A_data_in, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6]_PORT_B_data_in = SB1_ram_rom_data_reg[6];
RB1_q_a[6]_PORT_B_data_in_reg = DFFE(RB1_q_a[6]_PORT_B_data_in, RB1_q_a[6]_clock_1, , , );
RB1_q_a[6]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[6]_PORT_A_address_reg = DFFE(RB1_q_a[6]_PORT_A_address, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[6]_PORT_B_address_reg = DFFE(RB1_q_a[6]_PORT_B_address, RB1_q_a[6]_clock_1, , , );
RB1_q_a[6]_PORT_A_write_enable = GND;
RB1_q_a[6]_PORT_A_write_enable_reg = DFFE(RB1_q_a[6]_PORT_A_write_enable, RB1_q_a[6]_clock_0, , , );
RB1_q_a[6]_PORT_B_write_enable = SB1L62;
RB1_q_a[6]_PORT_B_write_enable_reg = DFFE(RB1_q_a[6]_PORT_B_write_enable, RB1_q_a[6]_clock_1, , , );
RB1_q_a[6]_clock_0 = CLK;
RB1_q_a[6]_clock_1 = A1L5;
RB1_q_a[6]_PORT_A_data_out = MEMORY(RB1_q_a[6]_PORT_A_data_in_reg, RB1_q_a[6]_PORT_B_data_in_reg, RB1_q_a[6]_PORT_A_address_reg, RB1_q_a[6]_PORT_B_address_reg, RB1_q_a[6]_PORT_A_write_enable_reg, RB1_q_a[6]_PORT_B_write_enable_reg, , , RB1_q_a[6]_clock_0, RB1_q_a[6]_clock_1, , , , );
RB1_q_a[6] = RB1_q_a[6]_PORT_A_data_out[0];

--RB1_q_b[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[6]
RB1_q_b[6]_PORT_A_data_in = VCC;
RB1_q_b[6]_PORT_A_data_in_reg = DFFE(RB1_q_b[6]_PORT_A_data_in, RB1_q_b[6]_clock_0, , , );
RB1_q_b[6]_PORT_B_data_in = SB1_ram_rom_data_reg[6];
RB1_q_b[6]_PORT_B_data_in_reg = DFFE(RB1_q_b[6]_PORT_B_data_in, RB1_q_b[6]_clock_1, , , );
RB1_q_b[6]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[6]_PORT_A_address_reg = DFFE(RB1_q_b[6]_PORT_A_address, RB1_q_b[6]_clock_0, , , );