代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
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vhd vhdl code6.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity HA is
port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC);
end HA;
architecture struct of HA is
component myXOR
port(in1,in2:in STD_LOGIC; out1:ou
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bak vhdl code6.bak
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity HA is
port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC);
end HA;
architecture struct of HA is
component myXOR
port(in1,in2:in STD_LOGIC; out1:ou
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vhd vhdl code5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1
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bak vhdl code5.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1'
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vhd vhdl code3.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY 4mux1 IS;
PORT(A,B,C,D:IN STD_LOGIC;
S0,S1: IN STD_LOGIC;
Q:OUT STD_LOGIC);
END 4mux1;
ARCHITECTURE behave OF 4m
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bak vhdl code3.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY 4mux1 IS
PORT(A,B,C,D:IN STD_LOGIC;
S0,S1: IN STD_LOGIC;
Q:OUT STD_LOGIC);
END 4mux1;
ARCHITECTURE behave OF 4mu
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pdf vhdl_use_tw.pdf
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prj uart_tx_vhdl.prj
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prj baud_gen_vhdl.prj
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