vhdl code5.bak

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT;
IF(RESET='1')THEN S<='0';
ELSIF T='1' THEN S<=NOT S;
END IF;
END PROCESS;
Q<=S;
QINV<=NOT S;
END behav;