vhdl code3.bak

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY 4mux1 IS
PORT(A,B,C,D:IN STD_LOGIC;
S0,S1: IN STD_LOGIC;
Q:OUT STD_LOGIC);
END 4mux1;
ARCHITECTURE behave OF 4mux1 IS
BEGIN
PROCESS(A,B,C,D,S0,S1)
BEGIN
IF S0='0' AND S1='0' THEN Q<='A';
ELSIF SO='1' AND S1='0' THEN Q<='B';
ELSIF SO='0' AND S1='1' THEN Q<='C';
ELSE Q<='D';
END IF;
END PROCESS;
END behave;
Output