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VHDL 的代码
test.udo
-- ProjNav VHDL simulation template: test.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
irda.npl
JDF E
// Created by ISE ver 1.0
PROJECT IrDA
DESIGN irda Normal
DEVKIT XCR3128XL TQ144
DEVFAM xpla3
FLOW XST VHDL
STIMULUS uart_tb.vhd Normal
STIMULUS irda_uart_tb.vhd Normal
MODULE txmit.vhd
makefile
LIBS = -Pcommon
build:
ghdl -m $(LIBS) $(TARGET)
scan: common/scan work/scan
%/scan:
ghdl -i --work=$* --workdir=$* $(LIBS) $*/*.vhdl
work/scan:
ghdl -i --mb-comments $(LIBS) *.vhdl
%/clean:
时序仿真.txt
查看Quartus 6.0的帮助文件，试验了一下可以进行时序仿真，以前看到过一些相关文章，但都没有成功，关键的一个问题就是没有编译库文件，总结步骤如下(本人用Verilog，括号中给出了用<mark>VHDL</mark>时的相关提示：
［注］Quartus版本为 6.0，ModelSim为 6.2a，其它版本可能稍有不同
方法一、根据Quartus帮助文件改写
1、File > Change Directo ...
microoven_bencher.prj
vhdl work "PICunit.vhd"
vhdl work "key_number_encoder.vhd"
vhdl work "counter.vhd"
vhdl work "clkdiv2.vhd"
vhdl work "clkdiv3.vhd"
vhdl work "seven_segnment.vhd"
vhdl work "microoven.vhd"
picunit.prj
vhdl work "PICunit.vhd"
microoven_tbw_bencher.prj
vhdl work "PICunit.vhd"
vhdl work "key_number_encoder.vhd"
vhdl work "counter.vhd"
vhdl work "clkdiv2.vhd"
vhdl work "clkdiv3.vhd"
vhdl work "seven_segnment.vhd"
vhdl work "microoven.vhd"
microoven.prj
vhdl work "PICunit.vhd"
vhdl work "key_number_encoder.vhd"
vhdl work "counter.vhd"
vhdl work "clkdiv2.vhd"
vhdl work "clkdiv3.vhd"
vhdl work "seven_segnment.vhd"
vhdl work "microoven.vhd"
clkdiv2.prj
vhdl work "clkdiv2.vhd"
picunit3_tbw_bencher.prj
vhdl work "PICunit.vhd"