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VHDL 的代码
jtop_vhdl.prj
vhdl work "D:\xjw\4_31\rom_16_8.vhd"
vhdl work "D:\xjw\4_31\ram_16_8.vhd"
vhdl work "D:\xjw\4_31\mux2.vhd"
vhdl work "D:\xjw\4_31\countern.vhd"
vhdl work "D:\xjw\4_31\jtop.vhdl"
vhdl_procedures.txt
这种电路设计要分好几个模块
主要思路是用ROM记录乐谱
然后用分频器分频
还有就是用计数器读取乐谱
另外还可以扩展 使其显示音符
我有一个做好了的 就是ROM没填谱
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-- Title: Music of Liangzhu --
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-- Data: 200
frequency_div.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fdiv is
Generic ( rate : integer :=10 );
Port ( f_in : In std_logic;
frequency_control.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control is
Port ( Bsignal : in std_logic;
Gate : out std_logic;
phase_meter.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Phase_Meter is
Port ( A : in std_logic;
B : in std_logic;
Clk : in std_logic;
O3 : out std_logic_vector(