frequency_control.vhdl

相位差测试

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control is
    Port ( Bsignal : in std_logic;
           Gate : out std_logic;
           Reset : out std_logic;
           latch : out std_logic);
end control;
architecture Behavioral of control is
  	signal G1,G2: std_logic:='0';
begin
process(Bsignal,G1)
  	begin
		if rising_edge(Bsignal) then
     	 	G1<=not G1;
		end if;
		if falling_edge(bsignal) then
			G2<=not G1;
		end if;	
end process;
		gate<=G1;
		latch<=G2;
		reset<=(not bsignal)and(not G1)and (G2);
end Behavioral;