phase_meter_testbench.vhd

来自「相位差测试」· VHDL 代码 · 共 77 行

-- VHDL Test Bench Created from source file phase_measure.vhd -- 15:32:07 06/20/2007
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY phase_measure_tb_vhd_tb IS
END phase_measure_tb_vhd_tb;

ARCHITECTURE behavior OF phase_measure_tb_vhd_tb IS 

	
                       
	                       COMPONENT phase_measure
	                       PORT(
		                       A : IN std_logic;
		                       B : IN std_logic;
		                       clk : IN std_logic;          
		                       BCD_3 : OUT std_logic_vector(6 downto 0);
		                       BCD_2 : OUT std_logic_vector(6 downto 0);
		                       BCD_1 : OUT std_logic_vector(6 downto 0);
		                       BCD_0 : OUT std_logic_vector(6 downto 0)
		                       );
	                       END COMPONENT;
                       
	                       SIGNAL A :  std_logic;
	                       SIGNAL B :  std_logic;
	                       SIGNAL clk :  std_logic;
	                       SIGNAL BCD_3 :  std_logic_vector(6 downto 0);
	                       SIGNAL BCD_2 :  std_logic_vector(6 downto 0);
	                       SIGNAL BCD_1 :  std_logic_vector(6 downto 0);
	                       SIGNAL BCD_0 :  std_logic_vector(6 downto 0);
                       
                       BEGIN
                       
	                       uut: phase_measure PORT MAP(
		                       A => A,
		                       B => B,
		                       clk => clk,
		                       BCD_3 => BCD_3,
		                       BCD_2 => BCD_2,
		                       BCD_1 => BCD_1,
		                       BCD_0 => BCD_0
	                       );
                       
                       
                       -- *** Test Bench - User Defined Section ***
                          tbclk : PROCESS
                          BEGIN
                             Clk <= '0';
	                        wait for 16 ns;
	                        Clk <= '1';
	                        wait for 16 ns;
                          END PROCESS;
                       
                          tbA : PROCESS
                          BEGIN
                             A <= '0';
	                        wait for 300000 ns;
	                        A <= '1';
	                        wait for 300000 ns;
                          END PROCESS;
                           
                          tbB : B <= A  after 150000 ns;
                       -- *** End Test Bench - User Defined Section ***
                       
     
END;