phase_meter.vhdl

相位差测试

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Phase_Meter is

Port ( A : in std_logic;
B : in std_logic;
Clk : in std_logic;
O3 : out std_logic_vector(6 downto 0);
O2 : out std_logic_vector(6 downto 0);
O1 : out std_logic_vector(6 downto 0);
O0 : out std_logic_vector(6 downto 0));

end Phase_Meter;


architecture Behavioral of Phase_Meter is

signal A1,B1,A2,B2,AP,BP,PD : std_logic := '0';
signal cnt14b_1,cnt14b_2 : std_logic_vector(13 downto 0) := (others => '0');
signal cnt12b : std_logic_vector(11 downto 0) := (others => '0');
signal EN,LD,Rst : std_logic := '0';
signal D3,D2,D1,D0 : std_logic_vector(3 downto 0) := (others => '0');

begin

process(Clk)
begin
if Clk'event and Clk = '1' then

------------ Phase_Detecter -------------- 
A1 <= A; A2 <= A1; AP <= A1 and (not A2);
B1 <= B; B2 <= B1; BP <= B1 and (not B2);
if AP = '1' then PD <= '1'; end if;
if BP = '1' then PD <= '0'; end if;

---------------- Ctrl --------------------
cnt14b_1 <= cnt14b_1 + 1; -- N计数，N=16384
if cnt14b_1 = "11111111111111" then -- 每4096N个时钟测量一次
cnt12b <= cnt12b + 1; 
if cnt12b = 0 then EN <= '1'; end if; -- EN从0开始 
if cnt12b = 3600 then EN <= '0'; end if; -- EN到3600N结束 
if cnt12b = "111100000000" then LD <= '1'; else LD <= '0'; end if; -- 在3840N时保存计数结果
if cnt12b = "111111110000" then Rst <= '1'; else Rst <= '0'; end if; -- 在4080N时清除计数结果
end if;

---------------- Count --------------------
if Rst = '1' then
cnt14b_2 <= (others => '0');
D0 <= (others => '0');
D1 <= (others => '0');
D2 <= (others => '0');
D3 <= (others => '0');
elsif EN = '1' and PD = '1' then
cnt14b_2 <= cnt14b_2 + 1; -- 进行N分频
if cnt14b_2 = "11111111111111" then
if D0 = "1001" then ---------------
D0 <= "0000"; --
if D1 = "1001" then --
D1 <= "0000"; --
if D2 = "1001" then --
D2 <= "0000"; --
if D3 = "1001" then --
D3 <= "0000"; --
else -- 相位计数
D3 <= D3 + 1; -- 采用10进
end if; -- 制BCD码,
else -- 计数范围
D2 <= D2 + 1; -- 到3600
end if; --
else --
D1 <= D1 + 1; --
end if; --
else --
D0 <= D0 + 1; --
end if; --
end if; --
end if; ---------------

------------- Latch & Decode ---------------
if LD = '1' then
case D0 is
when "0000" => O0 <= "0000001";
when "0001" => O0 <= "1001111";
when "0010" => O0 <= "0010010";
when "0011" => O0 <= "0000110";
when "0100" => O0 <= "1001100";
when "0101" => O0 <= "0100100";
when "0110" => O0 <= "0100000";
when "0111" => O0 <= "0001111";
when "1000" => O0 <= "0000000";
when "1001" => O0 <= "0000100";
when others => O0 <= "-------";
end case;
case D1 is
when "0000" => O1 <= "0000001";
when "0001" => O1 <= "1001111";
when "0010" => O1 <= "0010010";
when "0011" => O1 <= "0000110";
when "0100" => O1 <= "1001100";
when "0101" => O1 <= "0100100";
when "0110" => O1 <= "0100000";
when "0111" => O1 <= "0001111";
when "1000" => O1 <= "0000000";
when "1001" => O1 <= "0000100";
when others => O1 <= "-------";
end case;
case D2 is
when "0000" => O2 <= "0000001";
when "0001" => O2 <= "1001111";
when "0010" => O2 <= "0010010";
when "0011" => O2 <= "0000110";
when "0100" => O2 <= "1001100";
when "0101" => O2 <= "0100100";
when "0110" => O2 <= "0100000";
when "0111" => O2 <= "0001111";
when "1000" => O2 <= "0000000";
when "1001" => O2 <= "0000100";
when others => O2 <= "-------";
end case;
case D3 is
when "0000" => O3 <= "0000001";
when "0001" => O3 <= "1001111";
when "0010" => O3 <= "0010010";
when "0011" => O3 <= "0000110";
when "0100" => O3 <= "1001100";
when "0101" => O3 <= "0100100";
when "0110" => O3 <= "0100000";
when "0111" => O3 <= "0001111";
when "1000" => O3 <= "0000000";
when "1001" => O3 <= "0000100";
when others => O3 <= "-------";
end case;
end if; 

end if;
end process;

end Behavioral;