代码搜索结果
找到约 10,000 项符合
VHDL 的代码
clock.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use UNISIM.VComponents.all;
entity clock is
port(
clk: in std_logic;
RST: in std_logic;
T: out st
alu.vhdl
library IEEE;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
port(
T2: in std_logic;
vhdl.txt
5-1