alu.vhdl

16位cpu设计VHDL源码

library IEEE;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
 port(
 	T2: in std_logic;
	T3: in std_logic;
	clk: in std_logic;
	Rupdate: in std_logic;
	Radd: in std_logic_vector(2 downto 0);
	Rdata: in std_logic_vector(7 downto 0);
	IRout: in std_logic_vector(15 downto 0);
	MRD_C: out std_logic;
	MWR_C: out std_logic;
	Addr: out std_logic_vector(15 downto 0);
	ALUout: out std_logic_vector(7 downto 0));
end ALU;

architecture Behavioral of ALU is
component bufgp
	port(I: in std_logic; O: out std_logic);
end component;
type reg_vector is array(7 downto 0) of std_logic_vector(7 downto 0); --寄存器组
signal clkgp: std_logic;
signal regsters: reg_vector;
signal temp_A: std_logic_vector(7 downto 0); --A
signal temp_B: std_logic_vector(7 downto 0); --B
signal Addr_temp: std_logic_vector(15 downto 0); --addr
signal ALUout_temp: std_logic_vector(7 downto 0); --ALUout
begin
	u1: bufgp port map(I => clk, O => clkgp);
	process(T2, T3, clk, IRout)
	variable numi: integer := 0; --reg(Ri)
	variable numj: integer := 0;	--reg(Rj)
	variable temp_addr: std_logic_vector(15 downto 0); --R(7)//IR(7 downto 0)
	begin
		MRD_C <= '0';
		MWR_C <= '0';
		numj := conv_integer(IRout(2 downto 0));
		numi := conv_integer(IRout(10 downto 8));
		temp_A <= regsters(numi);
		temp_B <= regsters(numj);	
		Addr_temp(7 downto 0) <= IRout(7 downto 0);
		Addr_temp(15 downto 8) <= regsters(7);
		if(T2 = '1') then	  
			case IRout(15 downto 12) is
				when "0000" => ALUout_temp <= temp_A + temp_B; --ADD
				when "0001" => ALUout_temp <= temp_A - temp_B; --SUB
				when "0010" => ALUout_temp <= temp_A and temp_B; --AND 
				when "0011" =>	ALUout_temp <= temp_A or temp_B; --OR
				when "0100" => ALUout_temp <= temp_B; --MOV
				when "0101" => ALUout_temp <= IRout(7 downto 0); --MVI
				when "0110" => NULL;
				when "0111" => NULL;
				when others =>
					if(regsters(numi) = "00000000") then
						ALUout_temp <= (others => '0');
					end if;
			end case;
		elsif(T3 = '1') then 
			case IRout(15 downto 12) is
				when "0110" =>
					ALUout_temp <= temp_A;
					MWR_C <= '1';
					MRD_C <= '0'; --STA
				when "0111" =>
					MRD_C <= '1';
					MWR_C <= '0'; --LDA
				when others => NULL;
			end case;
		end if;
	end process;

	process(Rupdate)
	variable num: integer := 0;
	begin
		if(Rupdate = '1') then 
			 num := conv_integer(Radd);
			 regsters(num) <= Rdata;
		end if;
	end process;
	Addr <= Addr_temp;
	ALUout <= ALUout_temp;
end Behavioral;