clock.vhdl

16位cpu设计VHDL源码

library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use UNISIM.VComponents.all;

entity clock is
port(
	clk: in std_logic;
	RST: in std_logic;
	T: out std_logic_vector(4 downto 0));
end clock;

architecture Behavioral of clock is

component bufgp
	port(I: in std_logic; O: out std_logic);
end component;
signal clkgp: std_logic;

begin
	u1: bufgp port map(I => clk, O => clkgp);
	process(clkgp, RST)
	variable num: integer := 0;
	begin
		if RST = '0' then
			T <= "00000";
			num := 0;
		elsif clkgp = '0' and clkgp'event then
			if(num = 5) then 
				num := 0;
			end if;
			case num is
				when 0 => T <= "00001";
				when 1 => T <= "00010";
				when 2 =>	T <= "00100";
				when 3 => T <= "01000";
				when 4 => T <= "10000";
				when others => NULL;
			end case;
			num := num + 1;
		end if;
	end process;
end Behavioral;