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xhdl_misc.vhdl
--
-- Copyright Notice and Proprietary Information
--
-- Copyright (C) 1997-2000 X-Tek Corporation. All rights reserved. This Software
-- and documentation are owned by X-Tek Corporation, and may be
xhdl_bit.vhdl
--
-- Copyright Notice and Proprietary Information
--
-- Copyright (C) 1997-2000 X-Tek Corporation. All rights reserved. This Software
-- and documentation are owned by X-Tek Corporation, and may be
xhdl_bit.vhdl
--
-- Copyright Notice and Proprietary Information
--
-- Copyright (C) 1997-2002 X-Tek Corporation. All rights reserved. This Software
-- and documentation are owned by X-Tek Corporation, and may be
fenping_vhdl.prj
work fenping.vhdl
hour1.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour1 is
Port(clkh,reset:in std_logic;
--h1:in std_logic_vector(7 downto 0
hour11.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
top_vhdl.prj
vhdl work "D:\Project\Xilinx Project\My_Own\MyUart\transfer.vhd"
vhdl work "D:\Project\Xilinx Project\My_Own\MyUart\recv.vhd"
vhdl work "D:\Project\Xilinx Project\My_Own\MyUart\baud_gen.vhd"
vhdl w