hour11.vhdl

来自「EDA课程设计（带完整设计报告）」· VHDL 代码 · 共 20 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hour11 is
end hour11;

architecture Behavioral of hour11 is

begin


end Behavioral;