hour1.vhdl

来自「EDA课程设计（带完整设计报告）」· VHDL 代码 · 共 33 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour1 is
 Port(clkh,reset:in std_logic;
      --h1:in std_logic_vector(7 downto 0);              ――置数端（时）
      Hou1,hou2:buffer std_logic_vector(3 downto 0));        --时输出端
      --Enhour:out std_logic);              ――时计时器的进位，用来驱动星期计时器
End;
Architecture a of hour1 is
  Begin
 Process(clkh,reset)
  Begin
   If reset='0' then
       hou1<="0000"; 
       hou2<="0000";             --对时计时器清0
   -- Elsif set='0' then hour<=h1;                  ――对时计时器置h1的数
    Elsif clkh'event and clkh='1' then
       if (hou1= "0011" and hou2= "0010") then
           hou1<="0000"; 
           hou2<="0000"; 
     --重复计数       
       elsif (hou1= "1001")then
	     hou1<="0000";
	     hou2<=hou2+1;	   
       else
		  hou1<=hou1+1;
       end if;      
 end if;
End process;
End;