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VHDL 的代码
dds_vhdl.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.pin
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and a
signal4.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal4 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal4;
archite
signal3.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal3 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal3;
archite
signal2.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal2 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal2;
archite
signal1.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal1 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal1;
archite