signal2.vhdl

来自「一个简单的多种信号的发生器 包括正玄」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal2 is
port(clk,reset:in std_logic;
             q:out std_logic_vector(7 downto 0));
end signal2;
architecture a of signal2 is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
begin
if reset='0' then
   tmp:="00000000";
elsif rising_edge(clk) then
   if tmp="11111111" then
      tmp:="00000000";
   else 
      tmp:=tmp+1;
   end if;      
end if;
q<=tmp;
end process;
end a;