signal1.vhdl

来自「一个简单的多种信号的发生器 包括正玄」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity signal1 is
port(clk,reset:in std_logic;
             q:out std_logic_vector(7 downto 0));
end signal1;
architecture a of signal1 is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
variable   a:std_logic;
begin
if reset='0' then
   tmp:="00000000";
elsif rising_edge(clk) then
   if a='0' then
      if tmp="11111110" then
         tmp:="11111111";
            a:='1';
      else 
         tmp:=tmp+1;
      end if;       
   else
      if tmp="00000001" then
         tmp:="00000000";
            a:='0';
      else 
         tmp:=tmp-1;
      end if; 
   end if;
end if;
q<=tmp;
end process;
end a;