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VHDL 的代码
dds_vhdl.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.hif
Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1731
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-
dds_vhdl.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
pt
dds_vhdl.vhd
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity dds_vhdl is
port (clk: in std_logic;
suoding,as:out std_logic;
fword:in std_logic_vector(15 downto 0);
pwm_fpga.vhdl
Library IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY pwm_fpga IS
PORT ( clock,reset: in STD_LOGIC;
Data_value : in std_logic_vector(7 downto 0);
pwm
63_vhdl.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_gcd_disp is
end t