dds_vhdl.vhd

基于fpga的正弦波发生器设计

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity dds_vhdl is
	port (clk:	in	std_logic;
		  suoding,as:out std_logic;
		  fword:in	std_logic_vector(15 downto 0);
		  pword:in	std_logic_vector(7 downto 0);
		  fout :out	std_logic_vector(9 downto 0));
	end;
architecture one of dds_vhdl is
	component pll1
	PORT
	(
		inclk0		: IN STD_LOGIC;
		c0		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
	end component;
	component reg32b
		port(load,rst32:	in	std_logic;
			 din:	in	std_logic_vector(31 downto 0);
			 dout:	out	std_logic_vector(31 downto 0));	
	end component;
	component	reg10b
		port(	load,rst10:	in	std_logic;
				din:	in	std_logic_vector(9 downto 0);
				dout:	out	std_logic_vector(9 downto 0));
	end component;
	component adder32b	
		port(a:	in	std_logic_vector(31 downto 0);
			 b:	in	std_logic_vector(31 downto 0);
			 s:	out	std_logic_vector(31 downto 0));
	end component;
	component adder10b	
		port(a:	in	std_logic_vector(9 downto 0);
			 b:	in	std_logic_vector(9 downto 0);
			 s:	out	std_logic_vector(9 downto 0));
	end component;
	component sin_rom
		PORT
	(
		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
	end component;
	component  and2ab
			port(a,b:	in  std_logic;
			 	 clock0:out  std_logic);
	end component;
		signal f32b,d32b,din32b:	std_logic_vector(31 downto 0);
		signal p10b,lin10b,sin10b:	std_logic_vector(9 downto 0);
		signal cloc,cl,sd				:std_logic;
	begin
		f32b(21 downto 6)<=fword;
		f32b(31 downto 22)<="0000000000";
		p10b(9 downto 8)<="00";
		f32b(5 downto 0)<="000000";
		p10b(7 downto 0)<=pword;
		as<=cloc;
		suoding<=sd;
	u1:adder32b port map(	a=>f32b,b=>d32b,s=>din32b);
	u2:reg32b	port map(	dout=>d32b,din=>din32b,load=>cloc,rst32=>sd);
	u3:sin_rom	port map(	address=>sin10b,q=>fout,clock=>cloc);
	u4:adder10b	port map(	a=>p10b,b=>d32b(31 downto 22),s=>lin10b);
	u5:reg10b	port map(	dout=>sin10b,din=>lin10b,load=>cloc,rst10=>sd);
	u6:pll1 	port map(	c0=>cl,inclk0=>clk,locked=>sd);
	u7:and2ab		port map(	a=>cl, b=>sd,clock0=>cloc);
	end;