pwm_fpga.vhdl

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

		   Library IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY pwm_fpga IS
PORT   (  clock,reset: in  STD_LOGIC;
Data_value  : in  std_logic_vector(7 downto 0);
pwm      : out STD_LOGIC ) ; 
END pwm_fpga;

ARCHITECTURE arch_pwm  OF  pwm_fpga IS
SIGNAL reg_out : std_logic_vector(7 downto 0);
SIGNAL cnt_out_int: std_logic_vector(7 downto 0);
SIGNAL pwm_int, rco_int: std_logic;

function INC(X: STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is variable XV: STD_LOGIC_VECTOR(X'LENGTH - 1 downto 0); 
begin XV := X;
for I in 0 to XV'HIGH LOOP if XV(I) = '0' then XV(I) := '1' ; exit;
else XV(I) := '0' ; 
end if; 
end loop;
return XV; 
end INC;  

function DEC(X: STD_LOGIC_VECTOR) 
return STD_LOGIC_VECTOR is variable XV: STD_LOGIC_VECTOR(X'LENGTH - 1 downto 0); 
begin XV := X;
for I in 0 to XV'HIGH LOOP if XV(I) = '1' then XV(I) := '0' ; exit;
else XV(I) := '1' ; 
end if; 
end loop;
return XV;
end DEC;

BEGIN
-- 8-bit data register to store the data values .The data values -  will determine   the duty cycle of PWM output
PROCESS (clock,reg_out,reset)
BEGIN
IF (reset ='1') THEN
	reg_out <="00000000";
ELSIF (rising_edge(clock)) THEN
	reg_out <= data_value; END IF;
END PROCESS;

--8-bit up/down counter. Counts up or down based on the  pwm_int signal -and generates terminal count  whenever counter reaches the -maximum value or  when it transists  through zero. Terminal -count is uesd to automatically load the data value to generate --different pwm out with different duty cycle
--INC and DEC are the two functions which are used for up and --down counting, they are  defined in sepearate user_pakge library
PROCESS (clock,cnt_out_int,rco_int,reg_out) 
BEGIN
IF (rco_int = '1') THEN
cnt_out_int <= reg_out;
ELSIF  rising_edge(clock) THEN
IF (rco_int = '0' and pwm_int ='1' and cnt_out_int <"11111111") THEN 
cnt_out_int <= INC(cnt_out_int); 
ELSE
IF (rco_int ='0' and pwm_int ='0' and cnt_out_int > "00000000") THEN 
	cnt_out_int <= DEC(cnt_out_int); 
END IF; 
END IF;
END IF;
END PROCESS;

PROCESS(cnt_out_int, rco_int, clock,reset) BEGIN
IF (reset ='1') THEN rco_int <='1'; ELSIF rising_edge(clock) THEN
IF ((cnt_out_int = "11111111") or (cnt_out_int ="00000000")) THEN rco_int <= '1';
ELSE rco_int <='0';
END IF; END IF;
END PROCESS;

-- Logic to Generate the PWM ouput.
PROCESS (clock,rco_int,reset) BEGIN
IF (reset = '1') THEN
pwm_int <='0'; 
ELSIF rising_edge(rco_int) THEN
pwm_int <= NOT(pwm_int); 
ELSE
pwm_int <= pwm_int; 
END IF; 
END PROCESS; 
pwm <= pwm_int;

END arch_pwm;