pwmtest.map.summary

来自「利用VHDL实现CPLD（EMP240T100C5）的PWM输出」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Thu May 31 18:54:36 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : pwmtest
Top-level Entity Name : pwmtest
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 51
Total pins : 19
Total virtual pins : 0
UFM blocks : 0