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VHDL 的代码
flag.vhdl.bak
library ieee;
use ieee.std_logic_1164.all;
entity status_reg is
port ( clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
i : in std_logic_vector(3 downto 0)
ri.vhdl.bak
library ieee;
use ieee.std_logic_1164.all;
entity instr_reg is
port(
CLK : in std_logic;
ce : in std_logic;
rst : in std_logic;
instr :in std_logic_vector(15 downto 0);
cond : out std_log
testbenchri.vhdl.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity instr_reg_test is
end entity;
architecture arch of instr_reg_test is
signal done : boolean := false;
signal pass
fifo_vhdl.txt
-8x8 fifo VHDL 源代码
library ieee;
use ieee.std_logic_1164.all;
entity fifo_8x8 is
port( clock : in std_logic;
reset : in std_logic;
wr_req : in std_logic;
rd_req : in std
vhdl_example.html
VHDL程序范例
vhdl_delay.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:34 03/31/2007
-- Design Name:
-- Module Name: vhdl_delay
vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adiv is
port(clk:in std_logic;
rst:in std_logic;
y:out std_l