fifo_vhdl.txt

FIFO的VHDL编程

-8x8 fifo VHDL 源代码

library ieee;
use ieee.std_logic_1164.all;
entity fifo_8x8 is
   port( clock    : in std_logic;
   reset    : in std_logic;
   wr_req   : in std_logic;
   rd_req   : in std_logic;
         data_in  : in std_logic_vector(7 downto 0);
         full     : buffer std_logic;
         empty    : buffer std_logic;
         data_out : out std_logic_vector(7 downto 0));
end fifo_8x8;

architecture arch of fifo_8x8 is

   type type_2d_array is array(0 to 7) of std_logic_vector(7 downto 0);
   signal fifo_memory : type_2d_array;
   signal wr_address  : integer range 0 to 7;
   signal rd_address  : integer range 0 to 7;
   signal offset      : integer range 0 to 7;
   signal rd_signal   : std_logic;
   signal wr_signal   : std_logic;
   signal data_buffer : std_logic_vector(7 downto 0);
   signal temp        : std_logic_vector(4 downto 1);
begin

process(clock)
   begin
      wait until rising_edge(clock);
         temp(1) <= wr_req;
         temp(2) <= temp(1);
         temp(3) <= rd_req;
         temp(4) <= temp(3);
end process;

wr_signal <= temp(2) and not(temp(1));
rd_signal <= temp(4) and not(temp(3));  

offset <= (wr_address - rd_address)       when (wr_address > rd_address)  else
    (8 - (rd_address - wr_address)) when (rd_address > wr_address)  else
     0;

empty <= '1' when (offset = 0) else
   '0';
full  <= '1' when (offset = 7) else
   '0';

data_out <= data_buffer ;

 process(clock)
   begin
      if (clock'event and clock='1') then
       if reset = '1' then
         rd_address  <= 0;
          data_buffer <= (others => '0');
       elsif (rd_signal = '1' and empty = '0') then
          data_buffer <= fifo_memory(rd_address);
    case rd_address is
    when 7      => rd_address<=0;
     when others => rd_address <= rd_address + 1 ;
    end case;
       end if;
 end if;
   end process;


process(clock)
   begin
      if (clock'event and clock='1') then
       if reset = '1' then
          wr_address <= 0;
         elsif (wr_signal = '1' and full = '0') then
           fifo_memory(wr_address) <= data_in;
     case wr_address is
     when 7      => wr_address<=0;
     when others => wr_address <= wr_address + 1 ;
     end case;
         end if;
   end if;
   end process;

end arch;