vhdl1.vhd

来自「电子课程设计数字钟的源代码」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity adiv is
  port(clk:in std_logic;
       rst:in std_logic;
       y:out std_logic);
end adiv;

architecture behave of adiv is 
  signal qn :std_logic_vector(20 downto 0);
begin
 process(rst,clk)
 begin
   if rst='0' then 
       qn<=(others=>'0');
   elsif clk'event and clk='1' then
     qn<=qn+1;
   end if;
 end process;
 y<=qn(2);

end behave;