weisel.vhd

来自「电子课程设计数字钟的源代码」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity weisel is
  port(
       --k : IN STD_LOGIC;
       sel : in std_logic_vector (2 downto 0);
       weisel: out std_logic_vector (7 downto 0));
end weisel;
architecture module of weisel is
begin
process(sel)
  begin
case sel is
  when "000" => weisel<= "11111110";
  when "001" => weisel<= "11111101";   
  when "010" => weisel<= "11111011";
  when "011" => weisel<= "11110111";
  when "100" => weisel<= "11101111";
  when "101" => weisel<= "11011111";
  when "110" => weisel<= "10111111";
  when "111" => weisel<= "01111111";
  when others => weisel<= "11111111";
end case;
end process;
end module;