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dds_vhdl.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
dds_vhdl.hif
Version 7.1 Build 156 04/30/2007 SJ Full Version
36
2054
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
dds_vhdl.pss
|
b96e3240ddcd18f5bce4e426d4eb2a0
ADDER32B:u1
b804c20ea69e664c31eb8e21044b7d0
REG32B:u2
dea2e4d39331ccc2b51fb2b6135f28b0
sin_rom:u3
8c217f953f247f98fad176185fceb1ad
sin_rom:u3|altsyncram:altsy
dds_vhdl.qpf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
dds_vhdl.pin
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
dds_vhdl.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
clk_gen.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins