clk_gen.vhdl

来自「Direct Digital Synthesis (DDS),最好用的可步进的数」· VHDL 代码 · 共 31 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_gen is
		port(clk:in std_logic;--全局时钟
			  clk_scan:out std_logic);--扫描时钟  			  
end clk_gen;
		 --将16MHz的clk变为65536Hz
architecture Behavioral of clk_gen is
	  signal cnt:integer range 0 to 1;
	  signal clk_scanx:std_logic;
begin
	 process(clk)
	 begin
		 if(clk'event and clk='1') then
			 if(cnt=1) then
					  cnt<=0; clk_scanx<=not clk_scanx;
			 else cnt<=cnt+1;
			 end if;
		 end if;
	 end process;
	 clk_scan<=clk_scanx;
end Behavioral;