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VHDL 的代码
cpu_16.vhdl
library IEEE;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VComponents.all;
entity CPU_16 is
port(
CLK: in std_logic;
RST: in std_logic;
Dbus: inout std_logic_vector(15 dow
rev_vhdl.prj
work rev.vhdl
input_fm.vhdl
-- $Id: input_fm.vhdl,v 1.1.1.1 2005/01/04 02:05:56 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Input signal FM
-- Project : F
loop_filter.vhdl
-- $Id: loop_filter.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Loop filter component
-- Projec
phase_detector.vhdl
-- $Id: phase_detector.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Phase detector
-- Project
bench_xil.vhdl
-- $Id: bench_xil.vhdl,v 1.1.1.1 2005/01/04 02:05:56 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Test Bench For Xilinx
-- Project
vhdl10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vhdl10 IS
PORT( clk,reset: IN STD_LOGIC;
time : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
output : OUT STD_LO