📄 vhdl10.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vhdl10 IS
PORT( clk,reset: IN STD_LOGIC;
time : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY vhdl10;
ARCHITECTURE one OF vhdl10 IS
TYPE st IS (red,green,yellow);
SIGNAL c_st,n_st: st;
BEGIN
REG: PROCESS(reset,clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN
IF reset = '1' THEN c_st <= red;
ELSE c_st <= n_st;
END IF;
END IF;
END PROCESS;
COM: PROCESS(c_st,time)
BEGIN
CASE c_st IS
WHEN red =>
IF time = "010" THEN n_st <= green;
output <= "010";
ELSE n_st <= red;
END IF;
WHEN green =>
IF time = "100" THEN n_st <= yellow;
output <= "100";
ELSE n_st <= green;
END IF;
WHEN yellow =>
IF time = "001" THEN n_st <= red;
ELSE n_st <= yellow;
output <= "001";
END IF;
END CASE;
END PROCESS;
END one;
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