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VHDL 的代码
mti_vhdl.do
#----------------------------------------------------------
# Model Technology VHDL compiler script for the book
# Digital Signal Processing with FPGAs (2.edition)
# Author-EMAIL: Uwe.Meyer-B
vhdl.fc2
#----------------------------------------------------------
# Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2
# for the book: DSP with FPGAs (2. edition)
# Author-EMAIL: Uwe.Meyer-Baese@
vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
package p_alarm is
subtype t_digital is integer range 0 to 9;
subtype t_short is integer range 0 to 65535;
type t_clock_time i
vhdl源程序.txt
-- 整个电路系统的VHDL源程序
--CDKZQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CDKZQ IS
PORT(CLK_IN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CHOSE_KEY:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vhdl2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl2 is
port(clk:in std_logic;
clr:in std_logic;
dout:out std_logic);
end;
architecture one of vhdl2 is
sig