vhdl源程序.txt

多路彩灯控制原程序

-- 整个电路系统的VHDL源程序
--CDKZQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CDKZQ IS
  PORT(CLK_IN:IN STD_LOGIC;
        CLR:IN STD_LOGIC;
        CHOSE_KEY:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
        LED:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END ENTITY CDKZQ;
ARCHITECTURE ART OF CDKZQ IS
  COMPONENT SXKZ IS
    PORT(CHOSE_KEY:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
          CLK_IN:IN STD_LOGIC;
          CLR:IN STD_LOGIC;
          CLK:OUT STD_LOGIC);
  END COMPONENT SXKZ;
  COMPONENT XSKZ IS
    PORT(CLK:IN STD_LOGIC;
          CLR:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
  END COMPONENT XSKZ;
  SIGNAL S1:STD_LOGIC;
  BEGIN
   U1:SXKZ PORT MAP(CHOSE_KEY,CLK_IN,CLR,S1);
   U2:XSKZ PORT MAP(S1,CLR,LED);
END ARCHITECTURE ART;
--时序控制电路的VHDL源程序
--SXKZ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SXKZ IS
  PORT(CHOSE_KEY:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       CLK_IN:IN STD_LOGIC;
       CLR:IN STD_LOGIC;
       CLK:OUT STD_LOGIC);
END ENTITY SXKZ;
ARCHITECTURE ART OF SXKZ IS
  SIGNAL CLLK:STD_LOGIC;
  BEGIN
    PROCESS(CLK_IN,CLR,CHOSE_KEY) IS
    VARIABLE TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
    BEGIN
 IF CLR='1' THEN  --当CLR='1'时清零，否则正常工作
         CLLK<='0';TEMP:="0000";
      ELSIF RISING_EDGE(CLK_IN) THEN
        IF CHOSE_KEY="001" THEN 
          IF TEMP="0010" THEN
           TEMP:="0000";
            CLLK<=NOT CLLK ;
          ELSE
            TEMP:=TEMP+'1';
          END IF;
-- 当CHOSE_KEY="001"时产生基准时钟频率的1/2的时钟信号
        ELSIF CHOSE_KEY="010" THEN 
          IF TEMP="0011" THEN
            TEMP:="0000";
            CLLK<=NOT CLLK ;
          ELSE
            TEMP:=TEMP+'1';
          END IF;
-- 当CHOSE_KEY="010"时产生基准时钟频率的1/4的时钟信号
        ELSIF CHOSE_KEY="011" THEN 
          IF TEMP="0111" THEN
            TEMP:="0000";
            CLLK<=NOT CLLK ;
          ELSE
            TEMP:=TEMP+'1';
          END IF;
        ELSIF CHOSE_KEY="100" THEN 
-- 当CHOSE_KEY="011"时产生基准时钟频率的1/8的时钟信号
          IF TEMP="1100" THEN
            TEMP:="0000";
            CLLK<=NOT CLLK ;
          ELSE
            TEMP:=TEMP+'1';
          END IF;
-- 当CHOSE_KEY="100"时产生基准时钟频率的1/12的时钟信号
        ELSIF CHOSE_KEY="101"THEN 
          IF TEMP="1111" THEN
             TEMP:="0000";
             CLLK<=NOT CLLK ;
          ELSE
             TEMP:=TEMP+'1';
          END IF;
-- 当CHOSE_KEY="101"时产生基准时钟频率的1/16的时钟信号
        END IF;
     END IF;
   END PROCESS;
   CLK<=CLLK;
END ARCHITECTURE ART;
--显示控制电路的VHDL源程序
--XSKZ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XSKZ IS
  PORT(CLK:IN STD_LOGIC;
        CLR:IN STD_LOGIC;
        LED:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END ENTITY XSKZ;
ARCHITECTURE ART OF XSKZ IS
TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10);
  SIGNAL CURRENT_STATE:STATE;
  SIGNAL FLOWER:STD_LOGIC_VECTOR(23 DOWNTO 0);
  BEGIN
  PROCESS(CLR,CLK) IS
    CONSTANT F1:STD_LOGIC_VECTOR(23 DOWNTO 0):="000100010001000100010001";
    CONSTANT F2:STD_LOGIC_VECTOR(23 DOWNTO 0):="101010101010101010101010";
    CONSTANT F3:STD_LOGIC_VECTOR(23 DOWNTO 0):="001100110011001100110011";
    CONSTANT F4:STD_LOGIC_VECTOR(23 DOWNTO 0):="010010010010010010010010";
    CONSTANT F5:STD_LOGIC_VECTOR(23 DOWNTO 0):="100101001010010100101001";
    CONSTANT F6:STD_LOGIC_VECTOR(23 DOWNTO 0):="110110110110011011011011";
    CONSTANT F7:STD_LOGIC_VECTOR(23 DOWNTO 0):="111011101110111011101110";
    CONSTANT F8:STD_LOGIC_VECTOR(23 DOWNTO 0):="011000110001100011000110";
    CONSTANT F9:STD_LOGIC_VECTOR(23 DOWNTO 0):="100111001010010100101001";
   CONSTANT F10:STD_LOGIC_VECTOR(23 DOWNTO 0):="101111011110111101111011";
--十种花型的定义
    BEGIN
     IF CLR='1' THEN
       CURRENT_STATE<=S0;
     ELSIF RISING_EDGE(CLK) THEN
       CASE CURRENT_STATE IS
         WHEN S0=>
             FLOWER<="ZZZZZZZZZZZZZZZZZZZZZZZZ";
             CURRENT_STATE<=S1;
         WHEN S1=>
             FLOWER<=F1;
             CURRENT_STATE<=S2;
         WHEN S2=>
             FLOWER<=F2;
             CURRENT_STATE<=S2;
         WHEN S3=>
             FLOWER<=F3;
             CURRENT_STATE<=S4;
         WHEN S4=>
             FLOWER<=F4;
             CURRENT_STATE<=S5;
         WHEN S5=>
             FLOWER<=F5;
             CURRENT_STATE<=S6;
         WHEN S6=>
             FLOWER<=F6;
             CURRENT_STATE<=S7;
         WHEN S7=>
             FLOWER<=F7;
             CURRENT_STATE<=S8;
         WHEN S8=>
             FLOWER<=F8;
             CURRENT_STATE<=S9;
         WHEN S9=>
             FLOWER<=F9;
             CURRENT_STATE<=S10;
         WHEN S10=>
             FLOWER<=F10;
             CURRENT_STATE<=S1;
      END CASE;
   END IF;
  END PROCESS;
  LED<=FLOWER;
END ARCHITECTURE ART;