vhdl1.vhd

数字电子时钟中

   library ieee;
    use ieee.std_logic_1164.all;
    package p_alarm is
    subtype t_digital is integer range 0 to 9;
    subtype t_short is integer range 0 to 65535;
     type t_clock_time is array (5 downto 0) of t_digital;
     type t_display is array (5 downto 0) of t_digital;
     end package p_alarm;
     library ieee;
    use ieee.std_logic_1164.all;
    use work.p_alarm.all;
    entity counter is
      port (new_current_time:in t_clock_time;
            load_new_c,clk,reset:in std_logic;
            current_time:out t_clock_time);
            end entity counter;
            architecture art of counter is
            signal i_current_time:t_clock_time;
            begin
            process(clk,reset,load_new_c) is
            variable c_t:t_clock_time;
            begin
            if rising_edge (clk) then
            if reset = '1' then
             i_current_time(5) <=0;
             i_current_time(4) <=0;
             i_current_time(3) <=0;
             i_current_time(2) <=0;
             i_current_time(1) <=0;
             i_current_time(0) <=0;
            elsif load_new_c -'1' then
             i_current_time <=new_current_time;
             else
             c_t: i_current_time;
             if c_t(0) <9 then
                c_t(0) :=c_t(0)+1;
                else
                c_t(0) :=0;
             if c_t(1) <5 then
                c_t(1) :=c_t(1)+1;
                else
                c_t(1) :=0;
            if c_t(2) <9 then
                c_t(2) :=c_t(2)+1;
                else
                c_t(2) :=0;
           if c_t(3) <5 then
                c_t(3) :=c_t(3)+1;
                else
                c_t(3) :=0;
           if c_t(5) <2 then
           if c_t(4) <9 then
                c_t(4) :=c_t(4)+1;
                else
                c_t(4) :=0;
                c_t(5) :=c_t(5)+1;
                end if;
                else
              if c_t(4) <3 then
                 c_t(4) :=c_t(4)+1;
              else
                 c_t(4) :=0;
                 c_t(5) :=c_t(5)+1;
                 end if;
              else
                if c_t(4) <3 then
                c_t(4) :=c_t(4)+1;
                else
                c_t(4) :=0;
                c_t(5) :=0;
                end if ;
                end if ;
                 end if ;
                  end if ;
                   end if ;
                i_current_time <=c_t;
                end if;
                i_current_time <=c_t;
                end if;
                end if;
                end process;
                current_time <=i_current_time;
                end architecture art;