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VHDL 的代码
bootrom.vhdl
-- FILE NAME: bootrom.vhdl
-- ENTITY NAME: boot_rom
-- ARCHITECTURE NAME: behave
-- REVISION: A
--
-- DESCRIPTION: 128 byte x 8 bit ROM
-- to boo
vhdl.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2csyn is
port(
clk,reset:in std_logic;
scl:out std_logic;
ack_i,exnt_ack:buffer std_logic;
vhdl.txt
三人表决器BEGIN
--component instantiation statements.
--ports of component are mapped to signals
--within architecture by position.
gate1 : and2 PORT MAP (a, b, w1);
gate2 : and2 PORT